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1 of 70 optimum technology matching? applied gaas hbt ingap hbt gaas mesfet sige bicmos si bicmos sige hbt gaas phemt si cmos si bjt gan hemt functional block diagram rf micro devices?, rfmd?, optimum technology matching?, enabling wireless connectivity?, powerstar?, polaris? total radio? and ultimateblue? are trademarks of rfmd, llc. bluetooth is a trade- mark owned by bluetooth sig, inc., u.s.a. and licensed for use by rfmd. all other trade names, trademarks and registered tradem arks are the property of their respective owners. ?2006, rf micro devices, inc. product description 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . ordering information sdi sclk ldto vddrx txen ms/ txib mck/ txqb mdi/ txq ssb dcad rxen txst dac2 nc vcc vtc dac1 dcv2 vco2 gpo1 gpo2 osco oscom oscm vt vco1p oscb osca vdd bgdc vco1n ibin iin qin qbin fsr/ qout dri/ qbout enr/ iout clkr/ ibout vccv dcd txi drq/ gpo3 dcv1 gnd nc vco1 fin 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 adc adc lpf digital processing decimation downconversion channel filters standard serial interface digital vreg adc vreg ref. osc. serial programming interface control and calibration pa ramp control charge pump phase detector fractional divider gmsk modulator tx interface 10 dac 1 and dac 2 lpf dac dac output mux loop filters 3 vco2 vco1 vco vreg rf6001 fractional-n rf synthesizer with modulator and digital if filter the rf6001 is a combination synthesizer and signal processing ic, which along with the rf2722 very-low-if receive ic, constitutes rfmd's low-cost gsm trans- ceiver solution. the high-performance fractional-n synthesizer offers numerous fea- tures including a fully digital gmsk modulator with provisions for an analog i/q interface and extremely low current consum ption. the signal processor section pro- vides a digital receive filter path desi gned to complement the rf2722. the if inputs are digitized, filtered and downconverted to baseband i and q signals. the flexible baseband interface can be configur ed for either analog or digital operation. chip functionality is controlled through a th ree-wire serial data interface (sdi) bus. the rf2722 is part of the polaris tm total radio tm solution. features ? fractional-n synthesizer with digital gmsk modulator ? signal processing circuitry for use with rf2722 vlif receiver ? versatile baseband interface ? integrated rf transmit vco?s applications ? gsm/dcs handsets ? gsm/dcs/pcs handsets ? quad-band gsm handsets ? multi-band edge rx handsets ? multi-band gprs handsets rf6001 fractional-n rf synthesizer with modulator and digital if fil- ter rev a3 ds050929 9 part of the polaris? total radio? solution rohs compliant & pb-free product package style: qfn, 48-pin, 7 x 7
2 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution absolute maximum ratings parameter rating unit storage temperature -40 to +150 c input voltage, iin, ibin, qin, qbin 2.7 v input voltage, all others 3.6 v supply voltage, v cc -0.5 to 5.0 v supply voltage, v dd , v rxvdd , v ccv -0.5 to 3.6 v parameter specification unit condition min. typ. max. operating range all specifications met over listed operating range, unless otherwise specified. supply voltage (v rxvdd , v dd , v ccv , v cc ) 2.7 2.75 3.0 v temperature (t op ) -40 +25 +85 c frequency range receive cellular 850 869 894 mhz low band receive egsm900 925 960 mhz low band receive dcs1800 1805 1880 mhz high band receive pcs1900 1930 1990 mhz high band receive transmit cellular 850 824 849 mhz low band transmit egsm900 880 915 mhz low band transmit dcs1800 1710 1785 mhz high band transmit pcs1900 1850 1910 mhz high band transmit power supply supply current rx i rxd 30 ma digital interface supply current rx i rxa 34 ma analog interface supply current tx i txhgd 80 ma high band gmsk, digital supply current tx i txlgd 65 ma low band gmsk, digital supply current tx i txhga 80 ma high band gmsk, analog supply current tx i txlga 65 ma low band gmsk, analog supply current idle i mode1 5 ma reference and buffers on supply current idle i mode2 9 ma reference, buffer and afc dac supply current standby i sb 130 170 ua digital supply on, clocks off maximum current by pin v ddrx (pin 9) 14.5 tbd ma worst case mode of operation v cc (pin 18) 10.5 tbd ma worst case mode of operation v ccv (pin 24) 42.0 tbd ma worst case mode of operation v dd (pin 47) 11.2 tbd ma worst case mode of operation caution! esd sensitive device. the information in this publication is believed to be accurate and reliable. how- ever, no responsibility is assumed by rf micro devices, inc. ("rfmd") for its use, nor for any infringement of patents, or other rights of third parties, resulting from its use. no license is granted by implication or otherwise under any patent or patent rights of rfmd. rfmd reserves the right to change component cir- cuitry, recommended application circuitry and specifications at any time without prior notice. rohs status based on eudirective2002/95/ec (at time of this document revi- sion).
3 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution parameter specification unit condition min. typ. max. performance specifications sdi write to rxen or txst 200 ns delay from sdi write to rxen or txst rx_en to valid data start 200 sdcr mode 160 svlif mode tx_st to valid data start 140 s modulation accuracy tx rms phase error 1.1 3.0 tx peak phase error 5.0 7.0 tx 400khz gmsk spectrum -60 dbc 30khz rbw rel to mod peak vco1 external inductor q> 30. frequency range (f vco1 )824 915mhz phase noise at 20mhz (l f ) -164 dbc/hz power out 3 dbm frequency pushing 4 mhz/v v ccv + 0.15v frequency pulling 1 mhz 2:1 vswr all phases output vswr 2.5:1 vco2 frequency range (f vco2 )1710 1910mhz phase noise at 20mhz (l f ) -155 dbc/hz power out 3 dbm frequency pushing 4 mhz/v v ccv + 0.15v frequency pulling 1 mhz 2:1 vswr all phases output vswr 2.5:1
4 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution parameter specification unit condition min. typ. max. pll specification frequency range 0 2100 mhz internal 0 550 mhz fin pin input level (fin pin) 50 mv rms input impedance (fin pin) 2k //2pf on pc board phase detector frequency (f r )26mhz pll bandwidth 90 khz tx mode 50 khz rx mode phase noise at 50khz -80 dbc/hz rx mode -102 dbc/hz tx mode, vco1 -95 dbc/hz tx mode, vco2 output rf spectrum due to modu- lation 200khz -86.3 -83.3 dbc/hz 250khz -89.3 -86.3 dbc/hz 400khz -116.3 -113.3 dbc/hz low band 400khz -113.8 -110.8 dbc/hz high band 600khz to <1800khz -116.3 -113.3 dbc/hz 1800khz to <3000khz -126.5 -123.5 dbc/hz 3000khz to <6000khz -126.5 -123.5 dbc/hz > 6000khz -134.5 -131.5 dbc/hz total integrated noise 1 rms rx pll spurious outputs -65 dbc 600khz to 1.6mhz etsi spec limits -75 dbc 1.6mhz to 3mhz -85 dbc >3mhz low band -82 dbc >3mhz high band -108 dbc out of band pll warm-up time 140 stx mode 150 srx mode reference oscillator input vctcxo (osca pin) frequency range (f r )0 26mhz input level (v inr )250 mv rms input impedance (z inr )5k //2pf on pc board phase noise -150 dbc/hz at 100khz offset and above (external tcxo) reference oscillator input crystal (if used) beckmann curve discontinuities 0.2 ppm crystal startup time 1 ms crystal load capacitance 10.5 pf crystal case capacitance 2.5 4.0 pf pullability 30 ppm/pf
5 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution parameter specification unit condition min. typ. max. oscillator output buffer output voltage (v out )800 mv p-p load: 10k //10pf output frequency 13 26 mhz selected by oscom pin phase noise -115 dbc/hz ssb @ 50khz -120 khz ssb @ 100khz -125 dbc/hz ssb @ 400khz harmonic level -10 dbc 3rd harmonic -60 dbc 35th harmonic load resistance 10 k shunt load capacitance 5 30 pf shunt dac1 and dac2 specifications resolution (res d/a ) 12.5 14.0 bits effective number of bits sample rate (f s )26mhz lowpass filter bandwidth (bw d/a ) 120 128 136 khz lowpass filter order (n d/af )6 butterworth turn on time 15 swithin 10mv output noise floor 500 nv/rthz at 100khz offset offset error (v off )2040mv gain error (g error )tbd% output range (fs d/a )0.1 vcc-0.1v output resistive load (r d/a )30 k output capacitive load (c d/a ) 500 pf dac2 (afc) tri-state output impedance 160 k dac2en=0 rx adc specifications pins: iin, ibin, qin, qbin bandwidth (bw a/d )200 khz resolution (res a/d ) 12 13 bits effective number of bits input voltage (v cma/d ) 1.25 v common mode voltage input level (fs a/d )1v p-p measured differentially input impedance (z ina/d )30k single-ended sample rate (f1) 13 mhz
6 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution parameter specification unit condition min. typ. max. composite digital filtering and downconversion output word length 12 16 bits output word rate 13/48 13/12 mhz 100khz vlif mode passband ripple 1 db all bandwidths group delay composite with rf2716 43.0 43.2 43.5 us bw=80khz and 85khz 30.1 30.3 30.6 us bw=90khz and greater group delay variance 2 ns rf6001 only group delay variance at bandwidth edge worst case composite with rf2716 237 273 367 ns bw=80khz 250 289 409 ns bw=85khz 264 307 464 ns bw=90khz 281 330 538 ns bw=95khz 301 358 634 ns bw=100khz 360 443 911 ns bw=110khz 453 582 1321 ns bw=120khz 693 944 2108 ns bw=135khz 3db corner frequency composite with rf2716 80.0 mhz bw=80khz 85.4 mhz bw=85khz 87.2 mhz bw = 90 khz 94.0 mhz bw=95khz 97.2 mhz bw = 100 khz 107.8 mhz bw = 110 khz 118.3 mhz bw= 120 khz 133.3 mhz bw=135khz attenuation at -600khz -100 db all bandwidths attenuation at -400khz -60 db all bandwidths attenuation at -200khz -35 db bw=80khz and 85khz -40 db bw=90khz and 95khz -50 db bw=100khz and greater attenuation at +200khz -40 db bw=80khz and 85khz -55 db bw=90khz and greater attenuation at +400khz -100 db all bandwidths attenuation at +600khz -100 db all bandwidths
7 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution parameter specification unit condition min. typ. max. composite digital filtering and downconversion, cont?d. dcr mode passband ripple 0.5 db all bandwidths except 85khz 1.0 db bw=85khz group delay composite with rf2716 43.0 43.2 43.5 us bw=80khz and 85khz 30.1 30.3 3.06 us bw=90khz and greater group delay variance 2 ns rf6001 only group delay variance at bandwidth edge composite with rf2716 228 256 341 ns bw=80khz 241 271 369 ns bw=85khz 253 286 406 ns bw=90khz 267 303 456 ns bw=95khz 282 324 521 ns bw=100khz 325 383 720 ns bw=110khz 392 481 1035 ns bw=120khz 572 752 1750 ns bw=135khz 3db corner frequency composite with rf2716 80.8 mhz bw=80khz 85.4 mhz bw=85khz 89.8 mhz bw=90khz 96.5 mhz bw=95khz 100.1 mhz bw=100khz 110.2 mhz bw= 110khz 119.8 mhz bw=120khz 136.1 mhz bw=135khz attenuation at -600khz -100 db all bandwidths attenuation at -400khz -60 db all bandwidths attenuation at 200khz -35 db bw=80khz and 85khz -45 db bw=90khz and 95khz -50 db bw=100khz and greater attenuation at +400khz -100 db all bandwidths attenuation at +600khz -100 db all bandwidths
8 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution parameter specification unit condition min. typ. max. rx d/a converters pins: iout, ibout, qout, qbout resolution (res d/a ) 12 bits effective number of bits sample rate (fs) 13 mhz lowpass filter bandwidth (bw d/a ) 140 150 160 khz lowpass filter order (n d/af ) 6 hybrid butterworth/bessel iq differential offset 10 mv iq gain mismatch 0.1 0.5 db common mode voltage v ddrx /2 v output voltage range (fs d/a )0 2.0v p-p differential, 0db gain output resistive load (r d/a )30 k each signal output capacitive load (c d/a )50pfeach signal gmsk i/q interface pins: txi, txib, txq, txqb i/q input voltage (v cmi/q ) 1.00 1.25 1.50 v common mode i/q input level (v pi/q )0.51.01.20v pk differential input impedance (z ini/q )30 k digital input specifications apply to pins: ssb, sdi, sclk, rxen, txst, txen, mck, mdi, ms, oscm, oscom, clkr input high voltage (v ih )0.7v dd v input low voltage (v il )0.3v dd v input high current (i ih )50 a input low current (i il )50 a input setup time* (t su )10 ns input hold time* (t hld )10 ns input rise/fall time (t rfi )15ns input clock to select time (t cs )10 ns input clock pulse width high (t cwh ) 15 ns input clock pulse width low (t cwl )15 ns input capacitance (c in ) 650 ff digital output drivers apply to pins: ldto, enr, clkr, fsr, dri, mck, ms output high voltage (v oh )0.8v dd vwith 1ma load output low voltage (v ol )0.2v dd vwith 1ma load output rise/fall time (t rfo ) 5 ns with 20pf maximum load capacitance gpo output drivers apply to pins: gp01, gp02 and drq/gpo3. output high voltage (v oh )v dd -0.05 v with 1ma load v dd -0.45 v with 10ma load output low voltage (v ol ) 0.02 v with 1ma load 0.2 v with 10ma load * setup and hold times are measured from the time where the waveforms cross v dd /2.
9 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution pin function description interface schematic 1 iin non-inverting input of the i channel a/d converter, to be connected to i out of the rf2722. analog input. 2ibin inverting input of the i channel a/d converter, to be connected to ib out of the rf2722. analog input. 3qbin inverting input of the q channel a/d converter, to be connected to qb out of the rf2722. analog input. 4qin non-inverting input of the q channel a/d converter, to be connected to q out of the rf2722. analog input. 5txst transmit start. a rising edge on this signal initiates the transmit sequence (pa ramp up). a falling edge on this signal begins the transmit shut down sequence (pa ramp down). digital input with weak pulldown. 6gpo1 general purpose output 1. this pin can be used to control a t/r switch. general purpose digital output (gpo). 7gpo2 general purpose output 2. this pin can be used to control a t/r switch. general purpose digital output (gpo). 8dcad digital receiver, adc, and dac voltage regulator output. a decoupling capacitor is required to ground. dc output voltage of 2.5v when the receive circuits are enabled. 9vddrx receive power supply. supply filtering components may be required in some applications (e.g. series resist or and shunt capaci tor). note that series resistance to this pin will drop the supply voltage. the specified sup- ply voltage range needs to be present on this pin during operation. 10 oscb reference oscillator b input. when used with the internal reference oscilla- tor this pin is connected to an external 26mhz crystal. if an external tcxo is used, this pin should be floating. this pin possesses a dc voltage and may require a dc-blocking cap in some applications. dc voltage equal to vdd when the oscillator is off (oscm pin low); dc voltage of approximately 1v when used with a crystal; dc voltage of approximately 2.4v when used with a tcxo. analog input. 11 osca reference oscillator a input. when used with the internal reference oscilla- tor this pin is connected to an external 26mhz crystal. if an external tcxo is used, this pin should be connected to the tcxo output through a decou- pling capacitor. this pin possesses a dc voltage of approximately 1.25v and may require a dc-blocking capacitor in some applications. dc voltage equal to vdd when the oscillator is off (oscm pin low). analog input. 12 nc no connect. iin ibin qbin qin txst gpo1 gpo2 dcad vddrx pin 10 osca
10 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution pin function description interface schematic 13 bgdc bandgap voltage regulator output. a de coupling capacitor is required to ground. dc output voltage of 1.25v. 14 dac1 dac1 output. this pin is dedicated fo r the pa ramp control system when paen bit is set to logic 1. buffered analog output. 15 dac2 dac2 output. general purpose dac that can be used for afc control of the reference oscillator. buffered analog output. e 16 txen transmit enable. bi-directional digital pin. this pin can be used as an input or as an output of the pa ramp system. this signal is also used to enable the pa; for example, it should be connected to tx enable pin of the rf3146 pa. the direction of the pin is determined by the txenio bit. digital input with weak pulldown or digital output. 17 vtc vco coarse tuning control. this pin is connected to vtc pin on the rf2722 front end ic. digital output. 18 vcc pll power supply. supply filtering co mponents may be required in some applications (e.g., series resistor and shunt capacitor). note that series resistance to this pin will drop the su pply voltage. the specified supply volt- age range needs to be present on this pin during operation. 19 vt pll loop filter output. this pin should be connected to vt pin on the rf2722. provides the correct tuning voltage to set the rx vco to the pro- grammed frequency. low impedance analog output. 20 fin pll prescaler input. this pin should be connected to vco out pin on the rf2722. input impedance is specified in the pll section of the electrical specifications. when probing this pin, the probe must have an effective dc resistance of 180k minimum and <10pf capacitance. 21 nc no connect. 22 vco2 vco2 output. dcs/pcs vco output to the pa. this pin possesses a dc volt- age and may require a dc blocking cap in some applications. output impedance is specified in the vco2 section of the electrical specifications. 23 vco1 vco1 output. us cellular/egsm output to the pa. this pin possesses a dc voltage and may require a dc blocking cap in some applications. output impedance is specified in the vco1 section of the electrical specifications. 24 vccv vco power supply. supply filtering components may be required in some applications (e.g. series resistor an d shunt capacitor). note that series resistance to this pin will drop the su pply voltage. the specified supply volt- age range needs to be present on this pin during operation. bgdc dac1 pin 14 txen vtc vcc vt fin vco2 vco1 vccv
11 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution pin function description interface schematic 25 vco1n vco1 tank inductance, negative side. us ed to complete resonant circuit for vco1. refer to the applications section of the datasheet for details. 26 vco1p vco1 tank inductance, positive side. used to complete resonant circuit for vco1. refer to the applications section of the datasheet for details. 27 dcv1 vco1 regulator output. a decoupling capacitor is required to ground. dc output voltage of approximately 1.4v when vco1 is enabled. 28 gnd this pin should be tied to ground. 29 dcv2 vco2 regulator output. a decoupling capacitor is required to ground. dc output voltage of approximately 1.4v when vco2 is enabled. 30 oscom oscillator buffered output mode control. this pin controls the frequency of the osco (pin 48) output. a logic 0 on this pin results in 13mhz output and a logic 1 results in a 26mhz output. digital input with weak pulldown. 31 oscm oscillator mode control. this pin controls the internal reference oscillator mode as described in the reference os cillator section. digital input with weak pulldown. 32 drq/gpo3 digital serial rx data interface output for q data. this pin provides the q data while in digital rx interface mo de and rxmode(2:0) is set to 001 or 110. when s_mode is low or rxmode(2:0) is not equal to 001 or 110, this pin can be multiplexed and used as a third general purpose output(gpo3). this gpo can be used to contro l a t/r switch. digital output. 33 dri/qbout digital serial rx data interface output or qb analog output. this pin is mul- tiplexed between analog and digital rx output modes. the s_mode bit sets the interface mode. digital output or buffered analog output. 34 fsr/qout digital serial rx data interface frame sync or q analog output. this pin is multiplexed between analog and digital rx interface modes. the s_mode bit sets the interface mode. the rxfsb bit determines the direction of the pin in digital mode. digital input, digital output, or buffered analog output. 35 clkr/ ibout digital serial rx data interface clock or ib analog output. this pin is multi- plexed between analog and digital rx output interface modes. the s_mode bit sets the interface mode. the rxckb bit determines the direc- tion of the pin in digital mode. digital input, digital output, or buffered ana- log output. vco1n vco1p vco1n vco1p dcv1 dcv2 oscom oscm drq/ gpo3 dri/ qbout fsr/ qout clkr/ ibout
12 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution pin function description interface schematic 36 enr/iout digital serial rx data interface enable input or i analog output. this pin is multiplexed between analog and digital rx interface modes. the s_mode bit sets the interface mode. digital input or buffered analog output. 37 rxen receive path enable. receiv e circuitry is active when a logic 1 is applied to this pin. digital input with weak pulldown. 38 ldto lock detect/test digital output. this pin is multiplexed between various internal signals on the ic as defined by the tmux and ten bits. digital out- put. 39 sclk serial data interface clock input. digital input. 40 sdi serial data interface data input. digital input. 41 ssb serial data interface select input. the serial interface accepts clock and data when ssb is at a logic 0 (active low). digital input with weak pullup. 42 mck/txqb modulation clock input/output or txqb transmit analog input. this pin is multiplexed between analog and digital tx interface modes. the txad bit sets the interface mode. the txd_mode bit determines the direction of the pin in digital mode. digital input, digital output, or analog input. 43 mdi/txq modulation data input or txq transmit analog input. this pin is multiplexed between analog and digital tx interface modes. the txad bit sets the inter- face mode. digital input or analog input. 44 ms/txib modulation sync input/output or txib transmit analog input. this pin is multiplexed between analog and digital tx interface modes. the txad bit sets the interface mode. digital input/output or analog input. 45 txi txi transmit analog input. enr/ iout rxen ldto sclk sdi ssb vdd mck/ txqb mdi/ txq ms/ txib txi
13 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution packaging the device is packaged in a 48-pin leadless package with an outside dimension of 7mmx7mm and an exposed bottom-side ground flag. package drawing pin function description interface schematic 46 dcd digital voltage regulator output. a decoupling capacitor is required to ground. dc output voltage of 2.5v. 47 vdd digital power supply. supply filtering components may be required in some applications (e.g. series resistor an d shunt capacitor). note that series resistance to this pin will drop the su pply voltage. the specified supply volt- age range needs to be present on this pin during operation. 48 osco buffered reference oscillator output. this pin can be used to provide the system clock for the radio. analog output. dc output voltage of approxi- mately 1.6v when osco is enabled. dcd vdd osco 3.37 typ 3.50 typ -a- -b- 7.00 typ 6.75 typ 2 plcs 0.10 c a 2 plcs 0.10 c b 2 plcs 0.10 c a 2 plcs 0.10 c b -c- seating plane 0.08 c 0.90 0.85 0.70 0.65 0.05 0.00 5 notes: 1. shaded lead is pin 1. 2. die thickness allowable is 0.305 mm max. (0.012 inches max.). dimension applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip. 4. package warpage maximum 0.08 mm. applied for exposed pad and terminals. exlude embedding part of exposed pad from measuring. 5 3 0.30 0.18 0.10 c ab m 3 0.60 0.24 typ 0.60 0.24 typ 0.50 0.30 typ 5.25 4.95 sq 0.50
14 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution detailed functional block diagram sdi sclk ldto vddrx txen ms/ txib mck/ txqb mdi/ txq ssb dcad rxen txst dac2 nc vcc vtc dac1 dcv2 vco2 gpo1 gpo2 osco oscom oscm vt vco1p oscb osca vdd bgdc vco1n ibin iin qin qbin fsr/ qout dri/ qbout enr/ iout clkr/ ibout vccv dcd txi drq/ gpo3 dcv1 gnd nc vco1 fin 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 adc adc lpf digital processing decimation downconversion channel filters standard serial interface digital vreg adc vreg ref. osc. serial programming interface control and calibration pa ramp control charge pump phase detector fractional divider gmsk modulator tx interface 10 dac 1 and dac 2 lpf dac dac output mux loop filters 3 vco2 vco1 vco vreg
15 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution application information functional description the rf6001 is a highly integrated receive and transmit processor intended for gsm/gprs/edge rx applications. it contains the following functionality: a high performance fractional-n p ll, baseband digital filtering wi th a/d's and d/a's for gsm vlif reception, two power transmit vco's, gmsk modulator, pa ramp control dac, and oscillator afc control (reference oscillator cir- cuitry). the fractional-n synthesizer section is multiplexed betw een transmit and receive function s, creating two sets of pll parameters. pll10-pll12 registers are intended to be used with the receive vco on the rf2722 vlif receiver ic and pll20- pll21 registers are used with the two internal power vco's on the rf6001. each pll configuration has a fully integrated loop filter. the internal power vcos are designed for use in all gsm transmit bands; vco1 has a frequency range of 824mhz to 915mhz and vco2 has a frequency range of 1710mhz to 1910mhz. each vco has a +3dbm minimum output power. down conversion from vlif to baseband and all necessary baseband filtering for gsm/gprs/edge reception is implemented digi- tally, with programmable bandwidths ranging from 80khz to 135khz. the receive and transmit baseband interfaces can be configured to work with standard analog differential i/q si gnals or fully digital signals de pending on sdi programming. the gmsk modulator necessary for gsm signaling is also provided and feeds into the transmit fractional-n synthesizer for direct modulation of the vco's. there are also two d/as (dac1/dac2 ) provided; dac1 is configured to provide programmable ramp control for the pa, and dac2 for general-purpose dc tuning voltage applications. an automatic pa ramp control function is pro- vided, which has programmable ramp shaping and timing. features of the part include: ? a dc to 2.5ghz fractional-n pll having: ?fine frequency resolution (typically 1.55hz) ?charge pump with programmable curre nt capability and operation to 5v ?integrated loop filters ?low prescaler drive level requirement ? two integrated rf transmit power vco's with min +3dbm output power capability to drive pa's ? pa control system with gprs support ? power control dac for pa ramp generation and programmable dac for dc tuning voltage operation ? programmable digital or analog tx interface to fractional-n gmsk modulation system ? i and q channel digital filtering with 12-bit a/d's and d/a's for vlif reception ? i and q digital ssi interface with option for analog interface this device contains technology licensed under certain patents.
16 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution receive information composite filter responses the stopband frequency response is shown below for the 80 khz and 85khz channel bandwidt hs of the cascade of the rf2716/2722 and rf6001 in 100khz vlif mode. note the notch at 100khz. in this mode only the 80khz and 85khz band- widths have this notch. higher bandwidths may be used in this mode but a tone at 100khz will be present due to any residual dc components converted by the vlif offset. for the bandwidths of 90khz and greater, the dcr mode is suggest ed. residual dc errors will be present in the output in this mode. the stopband frequency response is shown below for the 100k hz and 110khz channel bandwidths of the cascade of the rf2716/2722 and the rf6001 in dcr mode. the stopband frequency response is shown below for the 120 khz and 135khz channel bandwidths of the cascade of the rf2716/2722 and the rf6001 in dcr mode.
17 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution the passband frequency is shown below for the 80khz, 85khz, 90khz, and 95khz channel bandwidths of the cascade of the rf2716/2722 and the rf6001 in 100khz vlif mode. the passband frequency is shown below for channel bandwidt hs of 100khz, 110khz, 120khz, and 135khz channel band- widths of the cascade of the rf2716/2722 and the rf6001 in dcr mode. baseband output interface the output of the digital filtering system can be selected to be a digital ssi interface or to be an analog i and q interface. the spi bit s_mode selects the digital mode if programmed high and selects the analog mode if programmed low. analog mode (s_mode=0) the block diagram presented below shows the interface in this mode of operation. the analog outputs are intended to interface directly with exis ting baseband ics which already contain 12 bit a/d converters. gsm/edge channel filter d/a converter clkr/ib out enr/i out chbw (2:0) gsm/edge channel filter d/a converter chbw (2:0) dr/qb out fsr/q out
18 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution due to the filters added to the d/a converter outputs, the grou p delay and channel bandwidths will be slightly modified. the plot below shows the amplitude response of the 80khz channe l bandwidth in 100khz vlif mode for the cascade of the rf2716/2722 and rf6001 with and without the d/a converter filter. the plot below shows the group delay response of the cascad e of the rf2716/2722 and the rf6001 with and without the d/a converter filter. as a second example, the same two plots are repeat ed for a channel bandwidth of 120khz in dcr mode. rx digital mode (s_mode=1) if s_mode is set true, the receiver baseband interf ace is configured to digital mode. in this mode: enr acts as the ssi bus enable pin. clkr acts as the clock output for the serial data transfer. fsr acts as the frame sync output for the serial data transfer. dri and drq are the serial data outputs. the following sections describe the various operational modes available.
19 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution selection of rx clocks and sync as inputs or outputs fsr can be configured as an input (rxfsb=1) or as an output (rxfsb=0). clkr can be configured as an input (rxckb=1) or as an output (rxckb=0). if clkr is an input, then: 1. there must be at least two clkr periods before valid data is output. 2. fsr can be an input or an output. 3. if fsr is also an input, then there must be at least two clkr periods before fsr is externally set. if clkr is an output then fsr must be an output as well. selection of rx sync location relative to data the position of fsr relative to the i channel msb can be set with the sdi bit fs_loc. if fs_loc is set false then the fsr pulse occurs with the msb of the i channel data as shown in all of th e diagrams in the digital rx ss i mode section below. if fs_loc is set true then the fsr pulse will occur on the cl ock immediately before the msb of the i channel data. selection of rx ssi enable method the digital rx ssi can be enabled by two methods. the first method is a physical pin labeled enr. if enr is set high then the rx ssi will activate two clkr pulses after enr rises. the sampli ng point of the digital filters is set by the position of rx_en rel- ative to the midamble and will not change with the position of enr. the sample time of the ssi output word will move with the edge of enr. if enr is set low then the rx ssi will deactivate after the current data transfer completes. this mode is active if the sdi bit en_sel is programmed low. if en_sel is programmed high then the rx ssi activates with rx _en high and deactivates with rx_en low. all timing edges are relative to rx_en. summary of digital rx ssi modes the various digital receive modes are explained in detail below. rxmode=000, dbl=0 in this mode the ssi provides one sample of i and one sample of q for each gsm symbol period. the output data pattern on dri is 12 bits of i data followed by 12 bits of q data followed by 24 blank bits. in this case fsr is (13/48)mhz=270.8333kbps and clkr is 13mhz. the various clkr modes are defined as follows: with clkrm=00 and rxckb=0, clkr will shut down after the q data transfer completes until the next i data transfer to save power; with clkrm=01 and rxckb=0, clkr is always enabled if enr is true; with clkrm=1x, clkr is always disabled. the following diagram summarizes this mode of operation. fs_loc=1 fs_loc=0 dri i(15) i(14) dri i(15) i(14) fsr fsr clkr clkr
20 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution rxmode=000, dbl=1 in this mode the ssi provides two samples of i and two sample s of q for each gsm symbol period. the output data pattern on dri is 12 bits of i data followed by 12 bits of q data. in this case, fsr is (13/24)mhz=541.667kbps and always marks the beginning of the i data transfer. clkr is 13mhz. the various clkr modes are defined as follows: with clkrm=00 and rxckb=0, clkr will shut down after the q data transfer completes until the next i data transfer to save power (with rxmode=000 and dbl=1, clkr will always be enabled as there is no blank data); with clkrm=01 and rxck b=0, clkr is always enabled if enr is true; with clkrm=1x, clkr is always dis- abled. the following diagram summarizes this mode of operation. rxmode=001, dbl=0 in this mode the ssi provides one sample of i and one sample of q for each gsm symbol period. the output data pattern on dri is 16 bits of i data followed by 32 blank bits, and the output data pattern on drq is 16 bits of q data followed by 32 blan k bits. in this case fsr is (13/48)mhz=270.8333kbps and clkr is 13mhz. the various clkr modes are defined as follows: with clkrm=00 and rxckb=0, clkr will shut down after the q data transfer completes until the next i data transfer to save power; with clkrm=01 and rxckb=0, clkr is always enabled if enr is true; with clkrm=1x, clkr is always disabled. the following diagram summarizes this mode of operation. 1 2 3 11 12 13 14 enr 15 23 24 25 26 48 12 tcs tcwh tcwl th clkr, clkrm=00 clkr, clkrm=01 fsr tsu drq dri i(11) i(10) i(1) i(0) q(11) q(10) q(1) q(0) i(11) i(10) 1 2 311121314152324 1 2 enr clkr, clkrm=00 or 01 fsr dri i(11) i(10) i(1) i(0) q(11) q(10) q(1) q(0) i(11) i(10) drq
21 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution rxmode=001, dbl=1 in this mode the ssi provides two samples of i and two sample s of q for each gsm symbol period. the output data pattern on dri is 16 bits of i data followed by 8 blank bits, and the output data pattern on drq is 16 bits of q data followed by 8 blank bits. in this case, fsr is (13/24)mhz=541.667kbps and always marks the beginning of the i and q data transfer. clkr is 13mhz. the various clkr modes are defined as follows: with clkrm=00 and rxckb=0, clkr will shut down after the q data transfer completes until the next i data transfer to save power; with clkrm=01 and rxckb=0, clkr is always enabled if enr is true; with clkrm=1x, clkr is always disabled. the following diagram summarizes this mode of operation. rxmode=010 in this mode the ssi provides one sample of i and one sample of q for each gsm symbol period. the output data pattern on dri is 16 bits of i data followed by 16 bits of q data. in this case, fsr is (8.667/32)mhz= 270.833kbps and always marks the beginning of the i data transfer. clkr is 8.667mhz. the various clkr modes are defined as follows: with clkrm=00 and rxckb=0, clkr will shut down after the q data transfer completes until the next i data transfer to save power (with rxmode=010, clkr will always be enabled as there is no blank data); with clkrm=01 and rxckb=0, clkr is always enabled if enr is true; with clkrm=1x, clkr is always disabled. dbl has no effect in this mode. the following diagram summarizes this mode of operation. dri i(15) i(14) i(1) i(0) i(15) i(14) clkr, clkrm=00 enr 1 2 3 15 16 17 18 19 47 48 1 2 clkr, clkrm=01 fsr drq q(15) q(14) q(1) q(0) q(15) q(14) enr 12 3 15 16 17 18 19 23 24 1 2 clkr, clkrm=00 clkr, clkrm=01 fsr dri i(15) i(14) i(1) i(0) i(15) i(14) drq q(15) q(14) q(1) q(0) q(15) q(14)
22 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution rxmode=011 in this mode the ssi provides one sample of i and one sample of q for each gsm symbol period. the output data pattern on dri is 16 bits of i data followed by 16 bits of q data follow ed by 16 blank bits. in this case, fsr is (13/48)mhz=270.833kbps and clkr is 13mhz. the various clkr modes are defined as follows: with clkrm=00 and rxckb=0, clkr will shut down after the q data transfer completes until the next i data transfer to save power; with clkrm=01 and rxckb=0, clkr is always enabled if enr is true; with clkrm=1x, clkr is always disabled. dbl has no effect in this mode. the following diagram summarizes this mode of operation. rxmode=100, dbl=0 in this mode the ssi provides one sample of i and one sample of q for each gsm symbol period. the output data pattern on dri is 16 bits of i data followed by 16 bits of q data followed by 64 blank bits. in this case fsr is (13/48)mhz=270.8333kbps and clkr is 26mhz. the various clkr modes are defined as follows: with clkrm=00 and rxckb=0, clkr will shut down after the q data transfer completes until the next i data transfer to save power; with clkrm=01 and rxckb=0, clkr is always enabled if enr is true; with clkrm=1x, clkr is always disabled. the following diagram summarizes this mode of operation. drq dri i(15) i(14) i(1) i(0) i(15) i(14) q(15) q(14) q(1) q(0) fsr clkr, clkrm=00 or 01 enr 12315 16 17 18 19 31 32 1 2 tcs tcwh tcwl th tsu 12 3 15 16 17 18 19 31 32 33 34 48 1 2 enr clkr fsr dri i(15) i(14) i(1) i(0) q(15) q(14) q(1) q(0) i(15) i(14) drq clkr clkrm=00 clkr clkrm=01 tsu th tcwl enr 12 3 15 16 17 18 19 31 32 33 34 96 1 2 tcs tcwh drq dri i(15) i(14) i(1) i(0) q(15) q(14) q(1) q(0) i(15) i(14) fsr
23 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution rxmode=100, dbl=1 in this mode the ssi provides two samples of i and two sample s of q for each gsm symbol period. the output data pattern on dri is 16 bits of i data followed by 16 bits of q data followed by 16 blank bits. in this case fsr is (13/24)mhz=541.667kbps and clkr is 26mhz. the various clkr modes are defined as follows: with clkrm=00 and rxckb=0, clkr will shut down after the q data transfer completes until the next i data transfer to save power; with clkrm=01 and rxckb=0, clkr is always enabled if enr is true; with clkrm=1x, clkr is always disabled. the following diagram summarizes this mode of operation. rxmode=101 (valid only for chbw greate r than or equal to 90khz in 100khz vlif or dcr mode.) in this mode the ssi provides four samples of i and four samp les of q for each gsm symbol period. the output data pattern on dri is 12 bits of i data followed by 12 bits of q data. in this case fsr is (13/12)mhz=1083.333kbps and clkr is 26mhz. the various clkr modes are defined as follows: with clkrm=00 and rxckb=0, clkr will shut down after the q data transfer completes until the next i data transfer to save power (with rxmode=101, clkr will always be enabled as there is no blank data); with clkrm=01 and rxckb=0, clkr is always enabled if enr is true; with clkrm=1x, clkr is always disabled. dbl will have no effect in this mode. the following diagram summarizes this mode of operation. tcwh tcs tsu th tcwl fsr dri i(15) i(14) i(1) i(0) q(15) q(14) q(1) q(0) i(15) i(14) drq clkr clkrm=00 clkr clkrm=01 enr 12 3 15 16 17 18 19 31 32 33 34 48 1 2 drq dri i(11) i(10) i(1) i(0) q(11) q(10) q(1) q(0) i(11) i(10) fsr clkr, clkrm=00 or 01 enr 12 3 11 12 13 14 15 23 24 1 2
24 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution rxmode=110 (valid only for chbw greate r than or equal to 90khz in 100khz vlif or dcr mode.) in this mode the ssi provides four samples of i and four samp les of q for each gsm symbol period. the output data pattern on dri is 16 bits of i data followed by 8 blank bits, and the output data pattern on drq is 16 bits of q data followed by 8 blank bits. in this case, fsr is (13/12)mhz=1083.333kbps and always marks the beginning of the i and q data transfer. clkr is 26mhz. the various clkr modes are defined as follows: with clkrm=00 and rxckb=0, clkr will shut down after the q data transfer completes until the next i data transfer to save power; with clkrm=01 and rxckb=0, clkr is always enabled if enr is true; with clkrm=1x, clkr is always disabled. dbl will have no effect in this mode. the following diagram summarizes this mode of operation. rxmode=111 (valid only for chbw greater than or equal to 90khz in 100khz vlif or dcr mode) in this mode the ssi provides four samples of i and four samp les of q for each gsm symbol period. the output data pattern on dri is 12 bits of i data followed by 12 bits of q data. in this case, fsr is (13/6)mhz=2166.67kbps and clkr is 26mhz. the various clkr modes are defined as follows: with clkrm=00 and rxckb=0, clkr will shut down after the q data transfer completes until the next i data transfer to save power (with rxmode=111, clkr will always be enabled as there is no blank data); with clkrm=01 and rxckb=0, clkr is always enabled if enr is true; with clkrm=1x, clkr is always disabled. dbl will have no effect in this mode. the first data field of 12 bits after enr rises will always be the i word. the following diagram summarizes this mode of operation. enr 12 3 15 16 17 18 19 23 24 1 2 clkr, clkrm=00 clkr, clkrm=01 fsr dri i(15) i(14) i(1) i(0) i(15) i(14) drq q(15) q(14) q(1) q(0) q(15) q(14) 12 3 11 12 13 14 fsr clkr clkrm=00 or 01 dri enr tsu th tcwh tcwl tcs 15 23 24 1 2 drq i(11) i(10) i(1) i(0) q(11) q(10) q(1) q(0) i(11) i(10)
25 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution all of the above diagrams assumed that rxckb=rxfsb=0. the diagram below presents an example with rxckb=1 and rxfsb=0. this is an external (baseband) cloc k with the fsr sync generated by the rf6001. note that the fsr pulse is located at the msb of the i word, an d that there will be two clkr pulses output before fsr rises. the same diagram will hold true with rxfsb=1 except in this case the sync is an input coming from the baseband part and the baseband must provide at least two clkr pulses before asserting fsr. if fs_loc=1 then the sync pulse is advanced by one clock cycle as shown below. dc offset correction fast fine dc adapt (ffda) the digital filters in the rf6001 perform a ?fast fine dc adapt? (ffda) which normally continues for about 50usec beyond the end of the cdca (coarse dc adapt on rf2716/2722), and results in a dc error of less than 80uv at the baseband interface. the ffda is triggered by the rx_en pin on the rf6001, which is normally exerted at the same time as the rx_en of the rf2716/2722. this means that the ffda runs during the cdca as we ll, but has little effect during that time. the total time that the ffda operates is set by rf6001 sdi fields dcad and dcad_2. during ffda, the clock rate to the dc correction system is 13mhz. the automatic operation of the ffda can be disabled by programming sdi bits aden=0 and aden_2=0. please note that, unlike with the cdca in the rf2716/2722, there is no way to activate the ffda in the rf6001 other than to assert a rising edge on rx_en. rx_mode=010 rxckb=1, fs_loc=0 drq dri i(15) i(14) i(1) i(0) i(15) i(14) q(15) q(14) q(1) q(0) q(1) q(1) fsr clkr enr 12 3 15 16 17 18 19 31 32 1 2 30 29 rx_mode=010 rxckb=1, fs_loc=1 clkr fsr dri i(15) i(1) i(0) i(15) i(14) q(15) q(14) q(1) q(0) q(1) q(1) drq enr 1215 16 17 18 19 31 32 1 2 30 29
26 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution slow fine dc adapt (sfda) normally, once the ffda timer has expired, the rf6001 fine dc co rrection system then holds the la st value calculated until the rx_en transitions to low at the end of the receive burst. howe ver, the system can be configured setting the sdi bits ad2en and ad2en_2 to continue operating after the ffda is complete d in a lower bandwidth mode called the slow fine dc adapt (sfda). in this mode, the internal adaptation update rate would no rmally be lowered by a factor of 48 to reduce the group delay distortion. this sfda rate is selected by the sdi fields adcl k and adclk_2, and is adjustable from the default of 13/48mhz up to 13mhz. once the fine dc adapt process is completed, the dc correction offsets internal to the rf6001 will be held until rx_en is no longer asserted, power is removed from the ic, or another slow adapt operation is scheduled. realistically, it is unlikely that the sfda mode will be used with gsm systems. this is because the sfda would convert a dc error into a slowly moving ac error. also , the gsm system will refresh the dc adapt on every frame, and thus a slow long term correction is not necessary. digital gain control sdi bits dagc (3:0) can be used as a digital gain control with a range from -18db to +60db. this may be used to keep the rf6001 i/q output voltages at a constant level for those baseband ic?s that require this functionality. blanking the receiver has two programmable blanking circuits. the first of these is controlled by the sdi field blk_dly and blanks the output of the channel filter so that the second dc offset corre ction block does not see the initial transients of the receiver. this reduces the amount of time needed to complete the second stage of the dc offset correction. the upper line in the diagram below shows the channel filter ou tput. the lower line shows the output of the blk_dly block as input to the second dc offset correction block. the second blanking circuit is controlled by the sdi field agc_ dly and blanks the i and q outputs. this avoids large startup transients being sent to the baseband pr ocessing. the diagram below shows the action of the agc_dly field on the output sig- nals.
27 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution as initial guidance for the settings of the dc offset and blan king system, the following two setups are presented. both are acceptable for gprs operation. the 160usec option represents a minimum startup time. the 210usec startup option will min- imize any dc errors due to initial thermal drift. transmit information transmit turn-on sequence the following diagram documents the transmit turn-on sequen ce when using the rf6001 wi th the rf3146 power amplifier. the sequence is initiated by taking txst signal high. the rf6001 requires 140 s worst case for all calibrations and pll lock to take place. once this is complete, the pa will be turned on by taking txen high (txenu=140 s). the pa ramp should start about 2 s later for optimal switching spectrum performance of the rf3146 (pat=142 s). there is a programming feature within the rf6001 to provide re al-time control of the front-end transmit/receive (t/r) switch. the t/r switch must be turned off during th e prior bust to ensure the etsi time-mask is not violated. this feature is invoked b y setting trd bit high. the gpo1, gpo2 and gpo3 outputs of th e rf6001 will be set to values programmed into trdc_tx(2:0) bits when txst is taken high. these values should turn off the t/r switch for the given transmit state. after time txenu, the gpo outputs of the rf6001 will revert back to the originally programmed states defined in sdi bits gpo1, gpo2 and gpo3. 160usec startup dctime1=20us dctime2=140us dcad=23h=129.2us blk_dly=1fh=114.5us agc_dly=2ch=162.5us dcad_2=25h=136.6us 210 usec startup dctime1=20us dctime2=180us dcad=30h=177us blk_dly=2ch=162.5us agc_dly=39h=210.5us dcad_2=32h=184.6us rf6001 turn on txst txen pa ramp txenu 140us startup time t=0usec rf6001 pa ramp completed burst starts t=-155usec activate rf6001 rf6001 gpo pins t=-140usec pa dac turn on t=-15usec pat pa ramp time gpo3 gpo2 gpo1 trdc_tx(2) trdc_tx(1) trdc_tx(0) gpo3 gpo2 gpo1
28 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution pa ramp control the rf6001 contains a pa ramp control system that operates th rough the dac1 pin. the pa ramp control system is turned on by programming paen bit to one (1). the user programs the mi nimum dac1 level into the dac1v register, the desired pa ramp waveform sample values into the par registers, and a gain word into the pag register. a conceptual block diagram of the pa ramp control system is illustrated below. the timing diagram below illustrates a gsm transmit burst. in th is case the gprs_tx1 bit is programmed to zero (0). the trans- mit vco and pll should be turned on and gi ven sufficient time to lock prior to starting modulation and the pa ramp. the mod- ulation and ramp sequence is initiated by taking the txst pin high. this starts the tx modulator (after a delay set by md_dly1), using data or modulation present on the gmsk modulati on interface or stored in the first in first out (fifo), and turns on dac1/vramp dac, set to the value in the dac1v register (the minimum value). (if modulation is not desired, the mod- ulation interface should be set to digital mode, and the tx input pins should be held inactive.) the txen pin is an output used to enable the pa. this pin will go high after the rising edge of the txst input pin with a delay programmed by the sdi field txenu. the pa ramp waveform starts after time pat relative to the rising edge of txst. the 16 steps in the par registers (paramp3- paramp11) are swept at a rate of (12/13) s with an interpolation by 2 to result in a rate of (6/13) s per step. dac1 remains at the maximum value of the pa ramp waveform until txst is taken low, at which point the par waveform is used to ramp the dac1 signal back down to the dac1v value. the dac and modulation shut off and the txen pin goes low after the ramp down is completed and following a delay programmed by the sdi field tx end. the dac1 signal is defined by the following equation: ramp lut par[15:0, 9:] pag(9:0) 10 10 dac1 pin 10 1 0 10 10 paen timer paen paen pat (7:0) 13mhz system clock 10 dac1en 10 dac1v(9:0) txst pin txen pin txenu (7:0) txend (5:0) txst pin dac pa ramp pag par ? 1024 ---------------------------- dac 1 v 65536 ------------------- - + 2.5 v ? =
29 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution the next diagram illustrates operation of the pa ramp contro l system for a gprs transmit sequence. in this case, the gprs_tx1 bit should be programmed to one (1), and gprs_tx2 is set to zero (0). as in the gsm burst case, the sequence is initiated by taking the txst pin high. the dac1 pin will ramp to the output level set by the par and pag settings. the new powe r level for the next gprs slot should then be programmed into the pag register. when txst is taken low and then high again, the system will ramp to the new value in the pag register, agai n using the waveform programmed into the par registers. (the change is initiated on the rising edge of txst.) this can cont inue indefinitely until a pag value of zero is programmed. the sy s- tem will then ramp down to the minimum (dac1v) value on the falli ng edge of txst. the txen pin will then return low after a delay set by txend after the ramp down has completed. dac output dac1v txenu txend tx_st tx_en standard gsm single burst (gprs_tx1=0, gprs_tx2=0) par[15]+dac1 pag* par [0] par [1] par [2] par [3] par [4] par [5] par [6] par [7] par [8] par [9] par [10] par [11] par [12] par [13] par [14] par [15] pat dac output dac1v pag(1)*par[15]+dac1v tx_en tx_st par[0] par[1] par[2] par[3] par[4] par[5] par[6] par[7] par[8] par[9] par[10] par[11] par[12] par[13] par[14] par[15] gprs mode 1 (gprs_tx1=1, gprs_tx2=0) pag(2)*par[15]+dac1v pag(3)*par[15]+dac1v pag (sdi) pag(1) pag(2) pag(3) pag(4)=0 txenu txend pat
30 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution a second gprs mode exists in the rf6001. setting gprs_tx1 to zero (0), and gprs_tx2 to one (1) activates this mode. in this mode, the dac is programmed to ramp down on the falling ed ge of tx_st, and then ramp back up on the next rising edge of tx_st. the next power level will change state on the rising ed ge of tx_st. this forces any phase discontinuities to occur at minimum output power and this avoids any spectral purity issues . this is similar in operation to non-gprs mode except that new parameters are loaded during the previous burst, and that the tx_en pin will not return lo w after a ramp down unless the next power level programmed is zero. to get one-eighth symbol time resolution (instead of full symbol resolution), md_dly2 may be used. md_dly2 is triggered when tx_st goes high between bursts. in fifo mode, once tx_s t is deasserted and the current bit cycle clock completes, the md_dly2 timer starts counting in one-eighth symbol resolution. during this time, the value stored in g_def will be sent to the modulator. when the md_dly2 counter times out, the fifo begins shifting out data again. seri al mode functions in the same manner except the serial bit clock stops during md_dly2 and starts once the timer expires. the diagram below shows this mode of operation. since the minimum guard time (center of last tail bit to center of first tail bit) can be as short as 32qst, the ramp time of 1 6qst down and 16qst up would be marginally too long to fit the g uard time. the sdi bit r1316b may be programmed high to shorten the ramp to be 13qst long instead of 16qst long. in this case , the ramp starts with par3 and ends with par15. the pre pro- grammed ramp accessed with rmpsel=1 is particularly convenient for use with this compressed ramp mode. the sdi bit r0816b, may be programmed high to shorten the ramp to 8qst instead of 16qst. in this case, the ramp starts with par1 and will use every other entry in the ramp table ending with par15. two different ramp shapes can be selected by appropriately setti ng the rmpsel bit. the default values of the par registers for each rmpsel setting are shown below. these defaults were chos en so that when used with the rf3146 power amplifier, the gsm time-mask and transient spectrum due to switching conf orm to etsi specifications. the defaults associated with rmpsel=0 should be used for egsm band, and the defaults a ssociated with rmpsel=1 should be used for dcs/pcs bands. user defined ramp shapes can be loaded into registers par0-par 15, they must be scaled to start at 000h (0) and end at 3ffh (1023) to work properly with the pa ramp system. rmpsel=0 rmpsel=1 dac output pat dac1 pag*par[15]+dac1 tx_en tx_st par[15] gprs mode 2 (gprs_tx1=0, gprs_tx2=1, r1316b=1) txend pag (sdi) pag(1) pag(2) pag(3)=0 par[15] txenu par[0] par[1] par[2] par[3] par[4] par[5] par[6] par[7] par[8] par[9] par[10] par[11] par[12] par[13] par[14] par[15] par[14] par[13] par[12] par[11] par[10] par[9] par[8] par[7] par[6] par[5] par[4] par[3] par[2] par[1] par[0] par[3] par[4] par[5] par[6] par[7] par[8] par[9] par[10] par[11] par[12] par[13] par[14]
31 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution gmsk modulation interface the gmsk modulation interface can be configured to accept analog i/q inputs or digital data bits with or without differential encoding. this interface multiplexes some of the same pins for analog and digital modes, and consists of the following: txi analog input (txi), txib analog input or modulation sync inpu t/output (txib/ms), txq analog input or modulation data input (txq/mdi), txqb analog input or modula tion clock input/output (txqb/mck), transmit enable (txen), and transmit start (txst). the sdi bit txad defines the state of the interface, if programmed false it will operate in analog mode and programmed true will operate in digital mode. if digital mode is selected , the txi input is disabled. the diagram below documents the gmsk modulation interface to the fractional synthesizer, showing all programmable sdi bits necessary for setup. the gmsk modulator block diagrams block performs the necessary pulse shaping to the decoded data bits in order to achieve gmsk modulation. since this is done in the digital domain, ther e is a delay associated with this block of approximately 14.1 s. the i and q transmit data should be sent early relative to the start of the burst to account for this delay. input analog or digital data may be differentially encoded in the rf6001 before the modulator. by setting the sdi bit tx_de high (1), input data is differentially encoded by the rf6001. in addition, the initial state of the internal differential encod er may be selected with the de_init bit. if the data has already been differentially encoded by the baseband, set the tx_de bit low (0 ). transmit modulation interface par0 000h 000h par1 000h 000h par2 029h 000h par3 076h 000h par4 0cdh 051h par5 128h 0c2h par6 183h 13fh par7 1dfh 1beh par8 23ch 237h par9 299h 2a8h par10 2f4h 30bh par11 349h 360h par12 393h 3a4h par13 3cdh 3d6h par14 3f2h 3f4h par15 3ffh 3ffh
32 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution digital mode programming the txad bit high puts the gmsk modulation interf ace in digital mode, and the txi input is disabled. the ms and mck signals can be generated by either the rf6001 or the baseband, as configured by sdi bit txd_mode. the data on mdi can be differentially enc oded by setting sdi bit tx_de true. if the data has already been differentially encode d by the baseband, the tx_de should be set false to bypass the differential encoder. tx_inv inverts the data at the outp ut of the differential encoder. the rf6001 also contains a 312 bit fifo. the fifo allows up to two timeslots of gmsk data to be loaded before the transmis- sion begins. addition of delay on mck the fifo needs a rising edge on mck to set the pointer before data is read on the falling edge of mck. if mck is inactive high then there is no rising edge on the first transfer as mck is already high. a rising edge is thus created by anding mck and ms. this is fine except at the end of the data transfer. at this point the base - band simultaneously drops ms to zero and returns mck to the inac tive high state. if mck occurs slightly earlier than ms then there will be a glitch pulse from the and of ms and mck and a ga rbage data bit will be read. as this is a situation of two digi tal signals changing simultaneously then unpr edictable behavior is to be expected. to fix this a 3nsec delay was added to mck with an sdi select in the spares field called mck_sel. this fixes the issue by insuring that ms falls before mck rises so there will be no glit ch. but this could be dangerous if the pc board layout adds del ay to ms relative to mck. the added delay could not be greatl y increased as the maximum tolerance delay would then cause an issue with the last valid data bit. case 1: gmsk clocking signals gene rated by baseband, txd_mode=1, txf=00 transmission is initiated by setting the txst or txen pins to a logical high. the baseband will generate a 13/48mhz clock that is applied to mck. if sdi bit txckinv is low, then on every rising edge of mck the baseband will assert an nrz data bit on mdi. the rf6001 will read this data on every falling edge of mck if txckinv is set. if txckinv is set high, the baseband will assert an nrz data bit on the falling edge of mck and the rf6001 will read this data bit on every rising edge of mck. the diagram below summarizes the operation of this interface. tx_inv phase adjust phadj tx_thp tx_thn fractional synthesizer clock analog interface digital interface tx_st tx_en txi txqb/mck txib/ms txq/mdi txad tx_de txf txckinv
33 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution case 2: gmsk clocking signals generated by rf6001, txd_mode=0, txf=00 transmission is initiated by setting the txst or txen pins to a logical high. the rf6001 will then respond by outputting a 13/48mhz clock on mck and a pulse on ms on every 16th mck pe riod. the baseband ic will respond with an nrz data bit on mdi at every rising edge of mck if sdi bit txckinv is low. the rf 6001 will read this data on every falling edge of mck if txck- inv is set low. if txckinv is set high, the baseband will assert an nrz data bit on the falling edge of mck and the rf6001 will read this data bit on every rising edge of mck. ms serves to synchronize the baseband ic by providing a new word pulse to refresh the output register of the baseband ic. the di agram below summarizes the operation of this interface. 12 3 4 5161 ms mck mdi txst/txen tsu th tcwh tcwl tcs tcs txckinv=0 12 3 4 5161 ms mck mdi txst/txen tsu th tcwh tcwl tcs tcs txckinv=1
34 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution case 3: gmsk fifo clocking signals generated by baseband, txd_mode=1, txf=01 the fifo will automatically clear under three conditions: 1) if the sdi reset field is programmed; 2) at the end of any transmi s- sion burst following the end of the ramp down; and, 3) if the sdi field fclr is set. this will clear the contents of the fifo m em- ory and designate the next bit written as the first output bit of the fifo. the baseband will then generate a clock of less tha n or equal to 26mhz applied to mck. on every rising edge of mck, the baseband will assert an nrz data bit on mdi if txckinv is low. the rf6001 will read this data on every falling edge of mck if txckinv is set low. if txckinv is set high, the baseband wi ll assert an nrz data bit on the falling edge of mck and the rf6001 will read this data if ms is high on every rising edge of mck. this data will be stored in a first in first out (fifo) register of length 1024 bits in the rf6001. the diagram below summarize s this part of the interface. transmission is initiated by setting the txst or txen pins to a logical high. if tx_st is set high, an internal timer (txenu) i s pro- grammed to delay the rise of tx_en. a second timer (md_dly) de termines then the modulation stored in the fifo will begin to be output relative to the rising edge of tx_st. data will be output at a 13mhz/48 rate. new data can be loaded into the fifo input while the output is active. the second diagram below summa rizes the operation of the second step of this interface. txckinv=0, txf=01 t su t h t cwh t cwl t cs mdi fifo count 123 4 mcko auto clear txckinv=1, txf=01 mcko auto clear fifo count 12 34 mdi
35 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution case 4: gmsk fifo clocking signals generated by baseband, txd_mode=1, txf=10 the fifo will automatically clear under three conditions: 1) if the sdi reset field is programmed; 2) at the end of any transmi s- sion burst following the end of the ramp down; and, 3) if the sdi field fclr is set. this will clear the contents of the fifo m em- ory and designate the next bit written as the first output bit of the fifo. the baseband will then generate a clock of less tha n or equal to 26mhz applied to mck. on every rising edge of mck, the baseband will assert an nrz data bit on mdi if txckinv is low. the rf6001 will read this data if ms is high on every falling edge of mck if txckinv is set low. if txckinv is set high th en the baseband will assert an nrz data bit on the falling edge of mck and the rf6001 will read this data bit if ms is high on every rising edge of mck. this data will be stored in a fifo re gister of length 1024 bits in the rf6001. the diagram below sum- marizes this part of the interface. this is the same as case 5 except that the data is framed by ms. transmission is initiated by setting the txst or txen pins to a logical high. if tx_st is set high then an internal timer, txen u, is programmed to delay the rise of tx_en. a second timer, md_dly, determines when the modulation stored in the fifo will begin to be output relative to the rising edge of tx_st. data will be output at a 13mhz/48 rate. new data can be loaded into the fifo input while the output is active. the second diagram below summarizes the operation of the second step of this interface. txckinv=0, txf=10 mdi fifo count 123 16 ms mck auto clear t su t h t cwh t cwl t cs txckinv=1, txf=10 auto clear mck ms fifo count 123 16 mdi
36 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution case 5: gmsk fifo clocking signals generated by baseband, txd_mode=1, txf=11 in this fifo mode, the baseband will generate a pulse equal to one clock period on the ms line to signify the beginning of a fifo data transfer. if the sdi bit ms_loc is programmed low then the transfer of the first data bit will occur on the same cloc k period as the pulse on ms. with ms_loc low there does not have to be any idle clock pulses between transfer intervals. if ms_loc is high then the transfer of the first data bit will occur on the next clock period after the pulse on ms. with ms_loc high there must be at least one idle clock pulse between the en d of the last transfer interval and the beginning of the next. the baseband will then generate a clock of less than or equal to 26mhz applied to mck. on every rising edge of mck, the baseband will assert an nrz data bit on mdi if txckinv is low. the rf6001 will read this data on every falling edge of mck if txckinv is set low. if txckinv is set high then the baseband will assert an nrz data bit on mdi on every falling edge of mck and the rf6001 will read the data bit on every rising edge of mck. this data will be stored in a fifo register of length 1024 bits in the rf6001. data will continue to be read in until the number of bits read becomes equal to the setting of the sdi word ms_len. ms_len can be set to 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16, 24, 32, or 48 bits. once this occurs, no further data will be read unti l another pulse is applied to ms to start the process over. the diagram below summarizes this mode of the interface. transmission is initiated by setting the txst or txen pins to a logical high. if tx_st is set high then an internal timer, txen u, is programmed to delay the rise of tx_en. a second timer, md_dly, determines when the modulation stored in the fifo will begin to be output relative to the rising edge of tx_st. data will be output at a 13mhz/48 rate. new data can be loaded into the fifo input while the output is active. the diagram below summa rizes the operation of the second step of this interface. note that there are not txd_mode=0 cases for the fifo system (i .e., the baseband is always the master of fifo data trans- fers.) txckinv=0, ms_len=4, txf=11 ms_loc=1 fifo count 1234 5 ms_loc=0 fifo count 1234 56 mck ms mdi txckinv=1, ms_len=4, txf=11 mck ms mdi fifo count ms_loc=0 1234 56 fifo count ms_loc=1 1234 5
37 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution analog i/q mode programming the txad bit low puts the gmsk modulation interface in analog mode. in this mode, programmable comparators are used to determin e the symbols contained in the i and q baseband waveforms at each symbol time. the positive and negative thresholds used for the differential i and q channel comparison are set by sdi bits tx_thp[3:0] and tx_thn[3:0] according to the following formulae. vth (positive)=0.05*(tx_thp+2) where tx_thp is the valu e between 0 and 15 that is programmed into that reg- ister. vth (negative)=-0.05*(tx_thn+2) where tx_thn is the value be tween 0 and 15 that is programmed into that register. each threshold should be set as close as possible to 0.625 times the peak differential i or q voltage. the following table indicates the appropriate threshold sdi settin gs for a given peak voltage of modulation waveform from the baseband. v pk from baseband (v) vth (v) recommended programming value th_thp[3:0] th_thn[3:0] 0.16 0.10 0 0 0.24 0.15 1 1 0.32 0.20 2 2 0.40 0.25 3 3 0.48 0.30 4 4 0.56 0.35 5 5 0.64 0.40 6 6 0.72 0.45 7 7 0.80 0.50 8 8 0.88 0.55 9 9 0.96 0.60 10 10 1.04 0.65 11 11 1.12 0.70 12 12 1.20 0.75 13 13 1.28 0.80 14 14 1.36 0.85 15 15 txenu md_dly pat pa ramp first bit into modulator tx_en tx_st transmission of data from the fifo
38 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution the phase of the symbol clock used to make i and q threshold deci sions will need to be set so that i/q sampling occurs at the maximum eye opening. ideally, the time measured from the maximu m eye opening to the rising edge of tx_st will be an inte- ger multiple of 3.69 s. this will assure that the rf6001 is sampling at the instance of maximum eye opening. if this time is not an integer multiple of 3.69 s, the phadj(5:0) bits will need to be set ac cording to the following procedure. enable the sample_iq pulse used by the analog interface to sample the i/ q waveforms with the following sdi settings, tsel(1:0)=01 and tmux(2:0) = 010. this pulse will be output on the ldto pin of the rf6001. program the phadj(5:0) bits to align the falling edge of this pulse with the maximum eye opening as shown in the diagram below: phadj(5:0) is adjustable from 0 to 63 (6-b it number) representing phase offsets from 0 s up to 4.846 s in approximately 77ns steps. as with the threshold settings, this phase will be sp ecific to a radio platform and needs to be determined by the user. also note that in tx mode dagc will affect the analog amplitude of the 8psk signal. dagc is expected to be set to 03h (for 0db gain) and should be programmed as such prior to a tx burst accordingly. detailed ramp-up the above development demonstrated the overall pa control me thodology. depending on the mode used within the rf6001 the detailed pa control methodology will now be developed. several sdi parameters must be properly set to properly ti me the ramp up. these parameters are as defined as follows: g_def (gmsk default) g_def will be the input value to the gmsk modulator when the modulator data input is not active. g_cnt (garbage count) the purpose of this sdi field is to allow the baseband to tr ansmit a programmable number of undefined bits at the beginning of each transmission. there are four possible modes of operation of this field depending on how the data is loaded into the rf6001. 1. fifo mode=00 when using fifo mode 00 the fifo is not active and the serial mode is active. if uam is true then g_cnt will begin when tx_st rises betw een two gprs bursts. the rf6001 will continue to fill data from g_def until g_cnt expires. ms will rise on th e last rising edge of mc k before g_cnt expires. th us the last mck during g_cnt is used to load data in the baseband register (if ms is used). if uam is false then g_cnt will be gin when md_dly2 expires in a tr ansition between two gprs bursts. g_cnt is not used on the first burst. the first 16 mck?s after md_d ly1 expires on the firs t burst ramp up will always be ignored and da ta will fill from g_def. 2. fifo mode =01 when using fifo mode 01 this field has no effect. (this is because we would have no way of knowing when the next group of fifo bits begins loading.) 3. fifo mode=10 when using fi fo mode 10 the ic will ignore the first g_cnt data bits oc curring on the first g_cnt mck cycles after ms rises. this affects only the fifo loading and has no effect in fifo read during actual trans- mission. 4. fifo mode=11 when using fifo mode 11 this field has no effect. iq waveform txst sample_iq phadj 1 0 1 tx_thp tx_thn
39 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution g_dly (gmsk delay) this field will increase the latency of the gmsk modulator in 1/16 symbol increments. the modulator delay can be adjusted from 12.2qst to 19.95qst. g_dly will hold the gmsk modulator in reset until g_dly expires. the data flow to the modulator is also delayed by the same amount. this will add latency to the gmsk modulator. during the reset time the data held in the gmsk modulator shift register is frozen and the output of the modulator is frozen. when g_dly expires then the shift register loads the new data bit that was present at the start of g_dly. the shift regi ster and modulator output are then released. the g_dly operation is performed on the occurrence of the first valid data bit of each time slot in a gprs transmission if ealgn is true. if ealgn is false then the g_dly operation is performed only at the first valid data bit of the first timeslot. ealgn the purpose of this bit is to realign the gmsk data flow to the trigger signal if the trigger signal is not on the symbol clock raster defined by the first rising edge of tx_st. if all timing is aligned to the symbol rast er then ealgn can be set to zero and timing advances based on the initial rising edg e of tx_st. in this case the guard time between gprs bursts will be an integer multiple of symbol times. this represents a timing slip of ? symbol from the etsi requirement. if this bit is true then the data clocks used for gmsk are rese t on the first valid data bit of each timeslot. in fifo mode the first valid data bit occurs when md_dly1 or md_dly2 time out. in seri al mode the first valid data bit occurs on the first falling mck edge after md_dly1 or md_dly2 expire. (g_cnt is ignored) if uam is true then md_dly2 is not used and the trigger point is then the rise of tx_st or md_dly1 expiring. when the clocks reset then a phase glitch will occur. in gmsk mo de the glitch will be at the modulator output at the end of the g_dly interval. this is because gmsk uses a lookup table system and thus resetting the clock glitches the output as soon as the g_dly parameter releases the output. ums (use ms) if this bit is set high then the first 16 mck data bits loaded after md_dly1 expires in serial mode will be filled with g_def a s opposed to loading data from the fifo or serial interface. this is used in serial mode with ms as the system needs to know to fill the first 16 bits with the default as the first ms is blanked. the 16 bits occur only on the first burst of a gprs transmi ssion. md_dly1 (modulation delay 1) this field sets the delay from the rising edge of tx_st to the beginning of the modulation. counter resolution will be 1/8 symbol time to allow the user to fine tune for the modulator latency. when tx_st rises the mod- ulators become active and receive data from the internal de fault data fields called g_def. when md_dly expires the gmsk modulator shifts from the default value to the input data stream. if fifo modes are used then the data flow from the fifo begins when md_dly1 expires. in serial mode if ms is active then the first ms after md_dly1 expires is blanked. thus there are always 16 mck pulses before the first rising ms. these first 16 pulses use the internal rf 6001 default values. in serial mode, md_dly1 only functions if mck is supplied by the rf6001.
40 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution gmsk ramp-up the diagram below presents the ramp up for gmsk in the fifo mode of operation. the latency is the sum of g_dly and the basic gmsk latency of 12qst. the sum of the two is 18qst and is selected to match the 8psk latency in this example. any glitch will occur when the clock resets at the end of g_dly and thus is at a low power level. this allows g_def to be used for the guard bits if desired. (note that 8qst ramps have been used for these examples; 13qst or 16qst ramps could be used equally well.) if data is loaded with the serial mode system using ms, then the diagram below presents the operation of the system. tx_en is set to occur 18qst before the top of the ramp so as to not violate the etsi time mask at the -30dbc point. md_dly1 is set to start the modulator 66qst plus g_dly before tx_en so that the first valid data symbol is the first tail symbol. g_cnt will have to be set to one in this case so that the initial st ate of the differential encoder is set at the correct time. if th e base- band differential encoding is us ed then g_cnt does not matter. note that the user could also send the g uard symbols if md_dly1 is further advanced. since the new data flow starts well in advance of the burst, th en there should be no issue with phase transitions if the delay from the rise of tx_st to the end of md_dly1 is not an integer nu mber of symbol times. any such transition will occur at mini- mum output power levels if md_dly1 is advanced far enough. pat txst dac1 txen pa turns on tail tail tail top of ramp 2qst modulator start 16qst first data from fifo clocks reset 12qst latency of gmsk mod complete txenu md_dly1 g_dly g_def data at rf fifo gmsk start-up mode, ealgn=1 pat txst dac1 txen pa turns on tail tail tail top of ramp 2qst modulator start mck starts 18qst max mck ms first valid data from baseband 6qst 12qst latency of gmsk mod complete txenu md_dly first ms pulse is always blanked 16 mcks 64qst g_dly modulator clock resets g_dly g_def data at rf serial gmsk mode using ms, mck and ms are output from rf6001, ealgn=1
41 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution controlling initial data flow the rf6001 can be configured to control th e dummy bits and guard bits that occur be fore the tail bits of the burst. the rf6001 can also be configured to allow the user to control these bits instead. the block diagram shown below is a useful representation of ho w the data flow works within the rf6001 for this functionality. the actual system has other control modes but for the purp oses of this discussion only this part is shown. tx_data is the data flow from the fifo or the serial interface de_init is the initial state of the differential encoder system set from sdi. clkx96 is the 26mhz system clock. sample_mdi is the internal trigger signal that reads tx_data gcnt_done is an internal trigger signal that si gnifies that the ?garbage count? is completed. tx_de selects internal differential encoding or not. g_def is the default states of the modulator when not selected for active data. md_dly1 triggers when active data is released to the modulators. d q d q tx_de 01 0 0 0 0 1 1 1 1 tx_data de_init clkx96 sample_mdi gcnt_done to gmsk modulator g_def 01 gcnt_done
42 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution control of guard bits using rf6001 in gmsk in gmsk mode etsi specifies that the guar d bits are all ones and the tail bits are all zeroes. this results in a differentially encoded output of 000000100ddddd. where ?d? represents the data bits. if tx_de is low then differential encoding is done in baseband. in this case de_init is held at zero and g_def is held at zero. the output to the gmsk modulator will be zero until md_dly1 expires. once md_dly1 expires then txdata will port to the gmsk modulator with differential encoding as defined by baseband . thus md_dly1 timing is set to switch over at the first tail bit. if tx_de is high then the differential enc oding is done within the rf6001. in this case de_init is held at one and g_def is hel d at zero. the output of the internal differential encoder will then be zero for the guard bits an d the internal state of the dif feren- tial encoder will be held at one during this time. when md_dly 1 expires then the input to the differential encoder will receive a zero for the first tail bit. this will encode with the internal state of one to an output of one at the differential encoder. subse- quent tail bits of zero will differentially encode with the pr evious state and result in zero. md_dly1 will be timed to expire at the first tail bit. note that when md_dly1 expires then this triggers gcnt to begin and all transitions actually occur when gcnt is done. if all bits are valid then gcnt is zero and gcnt_done is the same as md_dly1 expiring. also note that gcnt works on the output data flow only in serial input mode. in fifo mode gcnt works as the fifo is loaded but not when the fifo is read. thus gcnt is effectively zero in fifo mode for data output. control of guard bits using baseband in gmsk this is a fairly trivial case. md_dly1 is set to expire some time before the ramp up interval. the baseband sends data and by the time the transition from guard bits to tail bits occu rs the differential encoder ha s been initialized long ago. detailed gprs burst transition operation in a gprs transmission multiple timeslots can be transmitted. several sdi parameters must be properly set to properly time the transitions. these parameters are as defined as follows: (all of the previously defined parameters from the ramp up section still apply.) md_dly2 (modulation delay 2) in a gprs transmission, when tx_st falls at the end of the present tx timeslot, the data from the fifo stops and the value of g_def is used till md_dly2 expires. md_dly2 begins counting at the end of the present data bit being sent when tx_st falls. if uam is true then md_dly2 begins counting at the next rising edge of tx_st. data will continue to be taken from gdef until md_dly2 expires and then will switch to the fifo or the serial interface. uam (use alternate mode) the rf6001 has two modes of transitioning between gprs timeslot s. this first mode uses md_dly2 to trigger the data flow and tx_st edges to start the ramps. this is referred to as the ?normal? mode. if uam is set high then the ?alternate? mode of operation is activated. in this mode tx_st triggers the data flow. ramp up and ramp down are then controlled by two timers triggered from tx_st as described below. rd_dly (ramp down delay) rd_dly is a 5-bit field that will determine the start of the ramp down relative to the falling edge of tx_st in quarter symbol times (qst). this is only used if uam is true. ru_dly (ramp up delay) ru_dly is a 5-bit field that will determine the start of the ramp up relative to the rising edge of tx_st in qsts. this is only used if uam is true. in order to properly align the data upon making a transition between modes, the risi ng edge of tx_st must be aligned to the data stream.
43 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution gmsk to gmsk transitions gmsk to gmsk ealgn=1 ?normal? fifo mode this is the transition mode between two gmsk bursts in ?norma l? mode with ealgn set to one. any ?garbage? bits are blanked during the fifo loading process and have no effect during the transmit time. the rules for md_dly2 with uam=0 are as follows: 1. md_dly2 begins counting at the end of the curre nt symbol after tx_st falls on the first burst. 2. while md_dly2 is active, data is held in the fifo and the serial interface stops. when md_dly2 expires the next bit is released from the fifo and the effective fifo output clock has a rising edge. in serial mode mck has a rising edge on the last g_cnt after md_dly2 expires. 3. during the time md_dly2 is active the data at the output of the fifo or serial input is multiplexed to the sdi bit called g_def. 4. if md_dly2 is set to zero then md_dly2 is disabled. 5. when md_dly2 expires then g_cnt begins. (serial only) 6. on the last count of g_cnt, ms pulses. (serial only) 7. if md_dly2 is set to zero then g_cnt is ignored and ms will not pulse until the next normally occurring 16mck boundary. (serial only) if uam=1 then the rules change as follows: 1. md_dly2 begins counting after tx_st rises on the next burst. in this example, the rising edge of tx_st is aligned to be 8q st before the center of the first tail symbol. the modulator uses data loaded from the fifo. md_dly2 is set to one to cause a 1q st shift in the transition width and thus exactly meet the etsi 8.25 symbol guard time. once md_dly2 expires, the g_dly is set to 6qst. during the 6q st of g_dly the data at the modulator input is replaced by g_def. the output of the modulator is held at the guard value. at the end of g_dly, the tail bi t data present at the beginning of g_dly is fed to the modulator. the quarter-symbol shift will cause a phase transition to occur at the start of g_dly. this transition will occur during the ra mp down region and could be a problem. if the previous 4 symbol times are all 1, as shown in the diagram above, then the modu- lation is ?pinned? to maximum deviation and there will be no glitch when the clocks reset. also note that this transition does not exist for ealgn=0 and g_dly=0. 0 g_dly 0 0 1 1 1 1 1 1 1 1 0 01111 111000 1 1 1 12 qst 37qst g_dly center of last tail bit desired center of first tail bit 8qst md_dly2=1 clocks reset effective fifo output clock txst dac1 data at mod output tail tail tail data data tail tail tail guard g_def guard guard guard guard guard data at mod input guard guard tail data data guard tail guard g_def tail tail guard guard guard data at fifo output guard guard tail data data guard tail guard guard tail tail guard guard guard g_def
44 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution in gmsk mode, there is a latency of approximately 12qst (12.2q st, actually) from the center of a data symbol entering the modulator to the maximum rf effect of the symbol. thus dac1 is aligned with the ?data at output? field and is 12qst delayed from the data at the input of the gmsk modulator. the data at the input of the modulator is delayed by 6qst from the data at the fifo output by g_dly. thus the total delay is 18qst and matches the 8psk delay. note that none of the tail bits are punctured. gmsk to gmsk, ealgn=1, ?normal? serial mode if the serial mode interface is used instead of the fifo then the diagram below presents the transition. md_dly2 is active in serial mode as well as fifo mode. the rules for md_dly2 are as follows: data changes at mdi on the rising edges of mck and is read on the falling edges of mck. in this example g_dly is set to 6qst so the modulator input is delayed a net of 8 qst from the data at mdi. in this diagram g_cnt is set to three to blank the first three serial bits from the baseband system. md_dly2 is set to 1 to exactly meet the etsi 8.25 symbol guard time. g_def fill s the three garbage symbols and the 1 qst from md_dly2. there will be a phase glitch at the start of g_dly due to the quar ter bit shift. this will occur during the ramp down. as in th e last case this should not be a problem if the previous four symbols are all 1s or 0s. note that the falling edge of tx_st is delayed 1qst. this is not a timing mask issue as there is no timing mask between gprs bursts other than the maximum power level. if the serial mode interface is used with ms then the only difference is that ms will pulse on the last g_cnt count. 0 1 11 0 1 11 x 1 xx 0 1 0 0 1 00 0 00 0 00 0 mdi g_def garbage guard guard data guard guard data garbage garbage guard tail tail tail tail g_dly 12 qst g_dly 37qst center of last tail bit md_dly2=1 g_cnt=3 ignored garbage bits clocks reset 8qst desired center of first tail bit mck txst dac1 data alignment at rf guard tail tail tail data g_def g_def guard guard data tail tail tail modulator input guard guard tail tail guard g_def guard g_def data data tail tail tail
45 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution gmsk to gmsk ealgn=0, ?alternate? fifo mode the diagram below presents the transition between two gmsk timeslots in alternate mode. the falling edge of tx_st can be located in one of three position s to turn off the data after the last tail symbol of the first burst. rd_dly is adjusted depending on the qst chosen. the rising edge of tx_st is aligned to be 14qst before the center of the first tail symbol of the second burst so that the effective fifo clock starts at the correct time to align the first tail symbol to t he desired time. in gmsk mode there is a latency of approximately 12qst (12.2qst actually) from the center of a data symbol entering the mod- ulator to the maximum rf effect of the symbol. thus dac1 is aligned with the ?data at output? field and is 12qst delayed from the data at the output of the fifo. note that none of the tail bits are punctured. in this method of operation (ealgn=0) the rising edge of tx_s t for the second and later bursts must be an integer number of symbol times relative to the first rising edge of tx_st. the timing is aligned with the first rising edge of tx_st and will not change if subsequent tx_st transitions are aligned to this raster. (since g_dly is not zero then if txst moves off the raster t he system would realign the clocks as if ealgn=1.) this means that the guard time will be an integer number of symb ols and will ignore the quarter symbol shift specified by etsi. there will be no glitch in this mode. 12 qst 12 qst rd_dly= 11 qst to 13 qst center of last tail bit 36qst ru_dly= 6 qst center of first tail bit 14 qst first gmsk bit of next slot latency of gmsk mod complete no tail symbols punctured effective fifo output clock txst dac1 data at rf due to gmsk modulator tail tail tail data g_def tail data tail tail data at fifo output 0 0 1 tail tail tail data tail tail 11
46 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution gmsk to gmsk ealgn=1, ? alternate ? fifo mode the quarter symbol shift can be accounted for by setting ealgn to 1. the diagram below presents this situation. as before there will be a glitch at the rising edge of tx_st du e to the clock reset function causing a phase discontinuity. thi s occurs during minimum output powe r and should not be a problem. gmsk to gmsk ealgn=1, ? alternate ? serial mode if the serial mode interface is used instead if the fifo then the diagram below presents the transition. data changes at mdi on the rising edges of mck and is read on the falling edges of mck. in this diagram g_cnt is set to three to blank the first three serial bits from the baseband system. g_def fills the three gar- bage symbols. if the serial mode interface is used with ms then the only difference is that ms will pulse on the last g_cnt count. txst center of first tail bit tail tail tail center of last tail bit tail tail data data effective fifo output clock 0 first gmsk bit of next slot clocks reset tail 0 tail 22 qst 37qst tail g_dly 1 1 1 17 qst to 19 qst rd_dly= g_def 12 qst ru_dly= tail data tail tail 12 qst tail tail data tail tail tail tail g_dly g_def gmsk mod noise pulse due clock reset dac1 data at rf due to gmsk modulator data at fifo output data at gmsk mod input center of first tail bit center of last tail bit tail tail 34qst 37 qst 12 qst tail data data 0 tail 0 data data 19 qst tp 21 qst rd_dly= ru_dly= 26qst garbage x tail tail tail data data garbage bits g_cnt=3 g_def first gmsk bit for next slot garbage x garbage x g_def g_dly g_dly clocks reset tail tail tail tail tail tail tail tail tail gmsk mod noise pulse due clock reset txst dac1 modulator input mck mdi data at rf
47 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution transmit test mode there is a test mode in the rf6001 to assist in transmitter test ing. this mode is invoked by setting sdi bit txtest=1. pseudo- random data based on a pn9 sequence is used as the data sour ce to the gmsk modulator. the data sequence is initiated by a rising edge on txst and ends on the falling edge of txst . the transmit turn-on sequence defined in an earlier section should be followed to allow proper vco warm-up and pa ramping to take place when using this test mode. this test mode is shown in the diagram below: multiplexed rx and tx busses the rf6001 rx interface can be connected to the tx interface to result in a single interface to baseband as shown in the dia- gram below. regardless of the tx mode chosen the tx signals are all inputs and will not conflict with the rx signals. the rx outputs must be set to analog mode by programming s_mode low and holding rx_en low during transmit times. this is to avoid a conflict between the idle ground states of the digital rx outputs and the external txi and q signals. txdata txst pn9 data txi iout/enr txib/ms ibout/clkr txq/mdi qout/fsr txqb/mck qbout/dri tx_en txad phase adjust phadj tx_thp tx_thn tx_inv tx_de tx_st txf txckinv tx analog interface tx digital interface rx analog interface rx digital interface txenio txd_mode clkrm dbl rxfsb clkrinv rx_mode rx_en s_mode power on reset sdi fractional synthesizer clock rx digital ades tx_inv ms_len ms_loc rxckb en_sel rx_t
48 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution synthesizer information fractional-n synthesizer the rf6001 contains a charge-pump based, fractional-n phase locked loop (pll) for controlling the receive vco?s on the rf2722 and the transmit vco?s on the rf6001. the pll includes integrated loop filters and automatic calibration systems to counteract the effects of process and environmental variations, ensuring repeatable locktime and noise performance. the pll is intended to use a 26mhz reference frequency signal for operation within gsm cellular radio systems, but may be pro- grammed to use lower frequency reference signals if desired; ho wever, noise performance will degrade if a lower reference fre- quency is used. enabling the pll the pll can be enabled by the txst, txen, or rxen signals in ad dition to the pllen(1:0) bits. this allows automatic timing of the complete polaris chipset warm-up from a single pin in either tx or rx mode. the pll interfaces to both the integrated vco?s on the rf6001 or can interface to an external vco via the fin and vt pins. the vt_en and vcosel bits determine the mode of operation. when vt_e n is set to 0, the internal loop filter is disconnected from the vt pin. when vcosel(1:0) is set to 00, an external vco can be used with the input through fin. with vt_en set to 1, the internal loop filters are connected and the internal vco is se lected using the vcosel(1:0). with vcosel(1:0)=10, the inte- grated vco1 is active; with the vcosel(1:0)=11, the integrated vco2 is active. pll configuration the rf6001 pll provides options for use of internal and external vco?s, internal or external loop filter, automatic calibration s, etc. these settings require three 18-bit registers (54-bits). in order to provide rapid switchin g between operating modes, the serial interface provides four groups of ?pll preset? registers. each group contains three registers. the active pll preset reg is- ter group is determined by the pllsel(1:0) bits, as shown in the following table. the pll preset registers share the addresses 000101, 000110 and 000111. for example, if pllsel(1:0)=00, then the pll0x group is active, and address 000101 writes to pll00, address 000110 writes to pll01, address 000111 writes to pll02, and the pll will use the settings in pll00, pll01 and pll02. if pllsel(1:0)=10, then the pll2x group is active, these addresses write to pll20, pll21, pll22, and the pll will use the settings in these registers. loop filters the pll contains loop filters optimized for the vco?s it controls . the resistor and capacitor values of the loop filters (and t he dac filters) are calibrated by an rc calibration system that runs for up to 20 s when the plls or dacs are enabled. the rc_en bit in the cal register determines whether the rc calibrat ion system runs. it is recommended that the rc_en bit be set to true (1) always, to allow the system to run each time th e pll or dacs are enabled, to accommodate environmental varia- tions. the pll loop filter can be bypassed such that the vt pin will then be directly connected to the output of the pll charge pump, using the vt_en and lpf serial interface bits. in this manner, the pll can be used with an external vco and external loop filter. charge pump currents the pll employs a deadzone-free phase detector for fast, low-jitter locking performance. the base current in the charge pump can be selected using the cpi(0)bit. with cpi(0) set to 0, the charge pump is in a low current setting for use in receive mode with the rf2722. with cpi(0) set to 1, the charge pump is in a higher current setting for transmit mode with internal vco?s. pllsel(1:0) active pll preset register group 00 pll0x (pll00, pll01, pll02) 01 pll1x (pll10, pll11, pll12) 10 pll2x (pll20, pll21, pll22) 11 pll3x (pll30, pll31, pll32)
49 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution tuning gain calibration pll employs a tuning gain calibration algorithm to compensate fo r tuning gain variations in the integrated vco?s. this system eliminates loop gain and bandwidth variations across the vco tuni ng range, ensuring that the gsm spectral mask is met. it is recommended to set the kv_en bit to true (1) to allow the system to calibrate. calibration takes approximately 20 s after the loop has attained lock. lock detection the pll contains a lock detect circuit which can be routed to the ?lock-detect/test output? ldto pin via the test multiplexer. this circuit provides a rough indication of whether the pll is op erating properly. the ldto pin voltage will move from ground t o vdd when the loop is close to lock for several cycles of the l oop reference frequency. the ldto pin voltage will return to grou nd if the pll is out of lock. this signal can be monitored in tr ansmit mode to shut down the transmitter if the pll/vco system fails. frequency control the fractional-n pll provides very fine frequency resolution capa bility, requiring a total of 36 bits to set the frequency. in most cellular systems it is acceptable to have much coarser frequency control. fine frequency control can be separated into an afc (automatic frequency control) register. the frequency of the pll/vco is primarily determined by two regi sters: the offset register, offs(17:0); and, the afc register, afc(17:0). the offs register value programs the vco frequenc y in multiples of 5khz. with 18 bits, this gives a range of 2^18*5khz=1.31ghz. in order to cover all cellular bands, a base frequency is used, determined by the fbase(1:0) bits, as shown in the following table. the equation for the pll/vco frequency is: the change in frequency versus the afcd is as follows: each step on afcd will change the tx frequency (both bands) by in high band rx mode, the lo frequency will change by the same amount. in low band rx mode, the lo frequency will change by fbase(1:0) f base frequency range comment (freq. band) 00 0hz 0 to 1310.72mhz gsm/us cellular 01 832mhz 832mhz to 2142.72mhz dcs/pcs 10 1664mhz 1664mhz to 2974.72mhz dcs/pcs/w-cdma 11 1664mhz 1664mhz to 2974.72mhz dcs/pcs/w-cdma f vco f base offs 5 khz afcd 26 mhz 2 24 ------------------ ?? ?? + + = f afcd f reference 2 24 -------------------------------- ? = afcd 2 24 f reference -------------------------------- f ? = 26 mhz 2 24 ------------------ 1.55 hz 1 2 -- - 26 mhz 2 24 ------------------ 0.775 hz ?
50 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution note that the relationship between frequency error and afcd is reversed (negative) with high side injection receive mode. the afc register will provide fine tuning over a 203khz range for both tx bands and high band rx. for low band rx, the afc reg- ister will provide fine tuning over a 101.5khz tuning range. afcd(17:0) is an 18-bit twos complement signed value. 000000000000000000to011111111111111111=0(0hz) to 131071(203.16005khz)@1.55hz resolution. 111111111111111111 to 1 00000000000000001=-1(-1.55hz) to -13071(-203.16005khz) @ 1.55hz resolution. the host/dsp could decide to use the gsm channel number to generate the offs value. the base frequency in the rf6001 is different than that used by the etsi stan dard so an offset needs to be added, and the channel number needs to be multiplied by 40 to obtain the proper multiple of 5khz (gsm channels are in 200khz increments). for example, for e-gsm channel num- ber ?n?, the offs value may be calculated by: for 892.2mhz, e-gsm channel number 11, we obtain: using the above equation for f vco , we obtain note that 832mhz is 32 times 26mhz and 1664mhz is 64 times 26mhz. this may simplify calculations in the baseband pro- cessor. these calculations assume a 26mhz reference crystal fr equency. the 26mhz reference can be divided by 1, 2, or 4 internally in the rf6001 for use in the pll, and the frequency calculation will hold. if a different reference crystal frequenc y is used, the actual vco frequency will be calculated by multiplying f vco above by f xtal /26mhz. reference oscillator input a 26mhz system clock provided by crystal oscillator circuitry must be connected directly to the osca and oscb pins. all of the internal clocks, the osco buffered oscilla tor output, and the gated clock output on ldto are derived from the reference clock circuitry. the output of the dac2 pin is used to fine-tune the crystal oscillator frequency. the oscm pin is used to control the input buffer circuitry. when oscm=0, all input buffer circuitry is turned off. when oscm=1, the input buffer circuitry is turned on. oscm must be held low during power-up. instead of a crystal, a 26mhz system clock (tcxo output) can be connected to the osca pin through a decoupling capacitor. this pin possesses a dc voltage of approximately 1.25v. the output of the dac2 pin is used to fine tune the tcxo frequency. the figure below illustrates how a tcxo or crystal reference ca n be connected to the rf6001. only one of the two options may be used at one time. offs 40 n 890 mhz 5 khz --------------------- ?? ?? 40 n 178000 + = + = offs 40 11 178000 178440 = + = f vco 0 178440 5 khz 892.2 mhz = + =
51 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution clock outputs the osco output may be used to drive the rf2722, or it can provide the system clock for the radio. the oscom pin deter- mines the frequency of the buffered osco output signal. if oscom is low, the output signal is 13mhz. when oscom is high, the output signal is 26mhz. the rf2722 may also be provided a 26mhz clock from the ldto pin by setting the dc_clk bit true. this will output a 26mhz clock via the ldto pin for an amount of time set by dc_time3 after rxen is asserted. additional circuitry is included to prevent glitches, or incomple te pulses on the osco buffered output pin. this circuitry requ ires a few stable clock cycles before the output is enabled. vco?s the internal power vco?s on the rf6001 are completely integrat ed and controlled by the on-chip fractional-n pll. both low- band (vco1) and high-band (vco2) rf outputs can be matched to 50 with a single series capacitor. vco1 requires external inductors to ground of approximately 2.2nh with 5% tolerance and q> 30 on pins 25 and 26. using standard fr4 material (dk=4.25@1ghz, loss tangent=0.014) the inductor physical dimensions can be printed according to the table below based on the distance from top layer metal to rf ground plane: the output of the vco?s should be connected to the transmit buffers located in the rf2722, as shown in the diagram below: inductance (nh) line width (mils) line length (mils) gnd plane spacing (mils) 2.5 10 350 5 2.5 10 250 10 2.5 10 210 15 2.5 10 190 20 osca clock generation osco oscb tcxo internal clocks to host/dsp, and/or rf2722 dac2 crystal oscillator circuit *crystal used: toyocom pn tsx-8a, ndk pn 4025da *
52 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution general purpose output control the rf6001 provides three general purpose output pins, gpo1, gpo2, and gpo3; a timing control unit is implemented within the rf6001. this timing control is identical to that in the rf 2722 for the gpo?s with added gpo control in tx modes. the tim- ing controls are set by the dctime2 (11:0) and trd bits in the trsw register. the gpo values used during the startup of rx or tx bursts are defined by the trdcrx (2:0) and trdctx (2:0) bits in the cfg3 register. this allows the rf6001 to control the tx/rx switch to provide more isolation during dc offset correcti on in rx mode, or to provide more isolation for the pa output power before ramping up in tx mode. power supplies and control signals the rf6001 has four primary supply pins: v dd , v cc , v ccv , and v ddrx . these pins require a 2.7v to 3.0v supply, usually from a voltage regulator on the application circuit board. these four supply pins must be maintained within 0.3v of each other. that is, all four supplies should be power up or down together. the part is not designed to allow one supply to be at 2.7v to 3v wit h the others at 0v. the recommended start-up and power-on sequ ence for the rf6001 is described below. 1) power-down: all power supplies and enable lines are low (oscm, rxen, txst, txen). 2) standby mode: board regulators to v dd , v cc , v ccv , and v ddrx are enabled. all enable lines are low. the internal digital volt- age regulator (between v dd and dcd) requires approximately 50us to settle, triggering the internal power-on reset (por) cir- cuit. it is recommended that the base band processor send a reset op-code to the rf6001 at this point, as well. 3)idle mode: the reference oscillator input circuits and output buffer (osco) are en abled by setting the oscm pin high. the oscillator input and output circuits require up to 1ms to settle. 4) active mode (either receive or transmit): the required rece ive or transmit signal path and pll/vco circuits are enabled by the rxen or txst pin, respectively. to rf3146 27 pf 47 pf 28 27 21 23 22 26 25 24 loop filters vco2 vco1 vco vreg rf6001 18 17 13 12 rf2722
53 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution serial data interface and device control a three wire serial data interface allows user programming of th e internal control registers in the rf6001. the serial data int er- face consists of the serial select (ssb), serial data in (sdi ) and serial clock (sclk) pins. the lock detect/test out (ldto) pi n is by default configured as an output from the serial interface, but may be used to monitor variou s internal pll signals, as well. the serial interface contains a set of 32 18-bit regi sters that are individually accessed by 6-bit addresses. the figure below shows a timing diagram for a serial transfer to the rf6001 serial data interface. refer to the electrical spec i- fications for the timing margin requirements. the ssb pin is normal ly high. a serial transfer is initiated by taking ssb low. t he address and data bits on the sdi pin are shifted in on rising ed ges of the sclk pin, msb first. the data is latched and changes take effect on the falling edge of the clock pulse corresponding to the last (18 th ) data bit in the addressed register. if the trans- fer is interrupted, such that the 18th data bit clock pulse does not occur, then no data is written to the register. data may be written to the registers in two ways: one register per serial transfer, or several sequential (adjacent) registers per serial transfer. these actions are illustrated in the following figure. the serial interface provides the capability of reading from the registers. if a register is written while the ten sdi bit is s et to zero, then the previous contents of that register will be serially shifted out on the ldto pin. the following table illustrates th e rf6001 register map. a serial transfer is init iated on the falling edge of ssb, and serial data is shifted in msb first, starting with the register address and then the data. the reset opcode (011111) is unique in that once the 011111 opco de is written, the rf6001 is reset, and held in reset until the ssb pin is taken high. it is recommended to reset the rf60 01 upon initial power-up of the system by writing the 011111 serial interface opcode. this ensures that the part will start up with the default register settings and that it will not be dr awing current unless enabled. ssb sclk sdi tcwh tcwl th tcs tsu addr(5) addr(4) addr(0) msb lsb ... ... ... ... ... ... tcs tcs serial write, single address data17 data16 data2 data1 data0 addr5 addr4 addr1 addr0 data17 data16 data15 data2 data1 data0 ssb sdi sclk ldto address is automatically incremented to load the next register serial write, multiple, sequential addresses addr5 addr4 addr1 addr0 data17 data16 data15 data2 data1 data0 data17 data16 data15 data2 data1 data0 data17 data16 data2 data1 data0 data17 data16 data2 data1 data0 sdi sclk ssb ldto
54 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution the rmpsel bit in register parmp1 determines which set of pa ramp registers (parmp 3-11) is accessed for both serial trans- fers and pa ramping. if rmpsel=0, then a first set of 10 registers is accessed. if rmpsel=1, then the second set of 10 regis- ters is accessed by the same addresses. the individual registers and bits are described below. the default values are set upon reset and are binary unless notated with an h (hexadecimal). rf6001 register map serial transfer: msb lsb bit number:23222120191817161514131211109876543210 description address data configuration 1 (cfg1) 000000 cfg1(17:0) configuration 2 (cfg2) 000001 cfg2(17:0) configuration 3 (cfg3) 000010 cfg3(17:0) frequency offset (offs) 000011 offs(17:0) digital afc offset (afcd) 000100 afcd(17:0) pll x0 (pllx0) 000101 pllx0(17:0) pll x1 (pllx1) 000110 pllx1(17:0) pll x2 (pllx2) 000111 pllx2(17:0) tx modulation (txmod) 001000 txmod(17:0) pa ramp 1 (parmp1) 001001 parmp1(17:0) pa ramp 2 (parmp2) 001010 parmp2(17:0) pa ramp 3 (parmp3) 001011 parmp3(17:0) pa ramp 4 (parmp4) 001100 parmp4(17:0) pa ramp 5 (parmp5) 001101 parmp5(17:0) pa ramp 6 (parmp6) 001110 parmp6(17:0) pa ramp 7 (parmp7) 001111 parmp7(17:0) pa ramp 8 (parmp8) 010000 parmp8(17:0) pa ramp 9 (parmp9) 010001 parmp9(17:0) pa ramp 10 (parmp10) 010010 parmp10(17:0) pa ramp 11 (parmp11) 010011 parmp11(17:0) dac1 control (dac1) 010100 dac1(17:0) dac2 control (dac2) 010101 dac2(17:0) calibration (cal) 010110 cal(17:0) tr switch control (trsw) 010111 txtr(17:0) test (test) 011110 test(17:0) reset (reset) 011111 x(don?t care) calibration 2 (cal2) 110000 cal2 (17:0) ssi (ssi) 110001 ssi(17:0) blank (blank) 110011 blank (17:0) delay (delay) 110100 delay (17:0) d_fill (d_fill) 110101 d_fill (17:0) tx_dly (tx_dly) 110110 tx_dly (17:0)
55 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution configuration register 1 (cfg1)- address 000000 location bit name default function cfg1(17) smp_sel 0 selects the a/d rx sampler. use 0 for interface to an rf27ss with a common mode voltage of mid-supply 200mv. use 1 for interface to other front-ends with common mode voltage outside of this range. cfg1(16:15) pll_en(1:0) 00 pll enable method selection 0x=pll is enabled by rxen|txen|txst 10=pll is always disabled 11=pll is always enabled cfg1(14) uam 0 use alternate mode of pa ramping and data gating. if enabled, the ru_dly[4:0] and rd_dly[4:0] registers are used to delay the dac1 ramp up and ramp down, respectively, relative to the txst signal. in addition, user data is gated into the gmsk modulator while txst is high. while txst is low, g_def is gated into the modulator. 0=disabled 1=enabled cfg1(13) reserved 0 reserved, program to zero (0) cfg1(12) ums 0 if this bit is set high then the first 16 mck data bits loaded after md_dly1 expires in serial mode will be filled with g_dgf as opposed to loading data from the fifo or serial interface. this is used in serial mode with ms, as the system needs to know to fill the first 16 bits with the default as the first ms is blanked. the 16 bits occur only on the first burst of a multiburst transmis- sion. cfg1(11) mcksel 0 if programmed high, a nominal delay of 3nsec is added to the mck input. cfg1(10) reserved 0 reserved, program to zero (0) cfg1(9) gprs_tx2 0 enables gprs mode 2. in this gprs mode, the dac1 will ramp down before ramping to the next power level. between bursts, the ramp down is initiated by txst falling. the ramp up is initiated with txst rising. 0=gprs mode 2 disabled 1=gprs mode 2 enabled cfg1(8) gprs_tx1 0 enables gprs mode 1. in this gprs mode, the dac1 will ramp to the new power level without ramping down to low power. this mode supports the rf6001 legacy pa ramping modes. 0=gprs mode 1 is disabled 1=gprs mode 1 is enabled cfg1(7:5) rxmode(2:0) 000 digital rx interface mode 000=i and q data are multiplexed on the dri pin with 12-bit accuracy, 13mhz clock rate 001=i and q data are presented on the dri and drq pins with 16-bit accuracy, 13mhz clock rate 010=i and q data are presented on the dri pin with 16-bit accuracy, 8.667mhz clock rate 011=i and q data are presented on the dri pin with 16-bit accuracy, 13mhz clock rate 100=i and q data are presented on the dri pin with 16-bit accuracy, 26mhz clock rate 101=i and q data are presented on the dri pin with 12-bit accuracy, 26mhz clock rate 110=i and q data are presented on the dri and drq pins with 16-bit accuracy, 26mhz clock rate 111=same as 000 cfg1(4) s_mode 1 rx interface mode 0=analog mode 1=digital mode cfg1(3) dbl 0 ssi word rate 0 = ssi word rate is equal to the gsm symbol rate 1 = ssi word rate is equal to twice the gsm symbol rate cfg1(2:0) trdc_rx(2:0) 000 trd receive mode settings when rxen is high, {gpo3, gpo2, gpo1 pins}=trdc_rx(2:0) for a period defined by dc_time3, reverts back to normal gpo settings at the end of this time. when rxen is low, {gpo3, gpo2, gpo1 pins}={gpo3, gpo2, gpo1}.
56 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution configuration register 2 (cfg2)-address 000001 location bit name default function cfg2(17) vds 0 vlif or dcr select 0=vlif 1=dcr cfg2(16) qinv 0 inverts the q signal path. 0=uninverted, normal polarity 1=inverted polarity cfg2(15) iqswpi 0 swaps the i and q signal paths at the input to the digital vlif processor. 0=normal, unswapped 1=swapped cfg2(14) iqswpo 0 swaps the i and q signal paths at the baseband output of the digital vlif pro- cessor. 0=normal, unswapped 1=swapped cfg2(13) trd 0 transmit/receive gpo switch control. if programmed to 1 then the functionality described by trdc_tx and trdc_rx is activated. if programmed to zero then the gpo pins follow the gpo programming at all times. cfg2(12) aden 1 dc correction system enable 1=enabled 0=disabled cfg2(11) ad2en 1 dc correction system enable 2 0=dc correction system will continue to operate after the adapt time is elapsed, at the rate defined by adclk. 1=dc correction system will stop at the end of the adapt time. cfg2(10:9) adclk(1:0) 11 dc correction system clock rate, after adapt time is elapsed. default is 13mhz/48, for slowest adapt. 00=13mhz 01=13mhz/12 10=13mhz/24 11=13mhz/48 cfg2(8:3) dcad(5:0) 13h fine dc correction fast adapt time. programs in steps of (48/13) s. default is 70 s. cfg2(2:0) chbw(2:0) 010 selects the channel filter 3db bandwidth 000=80khz 001=85khz 010 = 90 khz 011=95khz 100=100khz 101 = 110 khz 110=120khz 111=135khz
57 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution configuration register 3 (cfg3)-address 000010 frequency offset regist er (offs)-address 000011 digital afc offset register (afcd)-address 000100 location bit name default function cfg3(17) gpo3 0 general purpose output pins. pins are set high or low as programmed, unless overridden by tr settings, controlled by trd, trdc_rx, trdc_tx, and the rxen and txen pins. cfg3(16) gpo2 0 cfg3(15) gpo1 0 cfg3(14:12) trdc_tx(2:0) 000 trd transmit mode settings. when txst is high, {gpo3, gpo2, gpo1 pins}=trdc_tx(2:0) for a period defined by txenu, reverts back to normal gpo settings at the end of this time. when txst is low, {gpo3, gpo2, gpo1 pins}={gpo3, gpo2, gpo1} cfg3(11:10) pllsel(1:0) 00 pll preset selection, determines the active set of pllxx registers. 00=pll00, pll01, pll02 registers are active 01=pll10, pll11, pll12 registers are active 10=pll20, pll21, pll22 registers are active 11=pll30, pll31, pll32 registers are active cfg3(9) reserved 0 reserved, program to zero (0) cfg3(8) reserved 0 reserved, program to zero (0) cfg3(7) rmpsel 0 pa ramp table select, determines the active set of pa ramp registers. 0=ramp table 0 is active 1=ramp table 1 is active cfg3(6) r1316b 0 changes the ramp up and ramp down time from 16quarter symbols to 13quarter symbols. 0=ramp time is 16qst 1=ramp time is 13qst cfg3(5) reserved 0 reserved, program to zero (0) cfg3(4) reserved 0 reserved, program to zero (0) cfg3(3:0) dagc(3:0) 3h digital gain control gain is equal to -18db+dagc*6db, from -18db to +60db. default is 0db. 0000=gain of -18db 0001=gain of -12db ... 1100=gain of +54db 1101=gain of +60db 1110=gain of +60db 1111=gain of +60db location bit name default function offs(17:0) offs(17:0) 0 pll frequency of fset the pll/vco lock frequency is determined by the equation: f vco =f base +offs*5khz+afcd*26mhz/2^24, where f base is set according to the f base (1:0) value, and afcd is set according to the afcd register value. see the afcd and pllx0 register descriptions. the rf6001 takes changes in r and vcodiv into account in the calculation of f vco . however, if the frequency present at the osca pin is not 26mhz, the vco frequency will be f vco ?=f vco *f ref /26mhz, where f vco ? is the actual vco frequency with a non 26mhz reference, and f ref is the actual fre- quency present at the osca pin. location bit name default function afcd(17:0) afcd(17:0) 0 digital afc offset adjustment for plls. this is a two?s component (signed) value. see the offs register description for more information on setting the pll/vco frequency.
58 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution pll register x0 (pllx0)-address 000101 pll register x1 (pllx1) - address 000110 location bit name default function pllx0(17) cpi_sw 1 charge pump current switch during calibration. 0=constant current 1=switches high during calibration pllx0(16) vt_en 0 vt pin enable 0=charge pump/internal loop filter are disconnected from vt pin 1=charge pump/internal loop filter are connected to vt pin pllx0(15) ld_en 0 lock detect enable for pll this must also be selected via the te st mux; see the test register descrip- tion for more information. pllx0(14) vtc_en 1 vco coarse tune enable 0=vco coarse tuning system is disabled 1=vco coarse tuning system is enabled pllx0(13) kv_en 1 kv calibration enable 0=disabled 1=enabled pllx0(12) lpfbw 0 loop filter bandwidth selector 0=external rx rf2722 1=internal tx vco?s pllx0(11) lpf 0 loop 1 filter bypass 0=internal loop filter is used 1 =internal loop filter is bypassed pllx0(10) cpl 0 charge pump leakage current 0=minimum value 1=2*minimum value pllx0(9) cpi 0 charge pump current 0=low current setting, used for rx with the rf2722 1=high current setting, used for tx with internal vcos pllx0(8) pdp 0 loop 1 phase detector polarity 0=negative, vco freq decreases with increasing tuning voltage, used for rx with the rf2722 1=positive, vco freq increases with increasing tuning voltage, used for tx with the internal vcos pllx0(7:6) p(1:0) 00 prescaler modulus the prescaler is set as follows: 0x=prescaler is bypassed, (0mhz to 500mhz at prescaler input) 10=4/5 mode (494mhz to 2ghz at prescaler input) 11=8/9 mode (1.95ghz to 2.5ghz at prescaler input) pllx0(5:4) vcosel(1:0) 00 vco select 00=external vco, fin pin is used as input 10=integrated vco1 11=integrated vco2 pllx0(3:2) vcodiv(1:0) 00 vco post divider 0x=the vco is directly coupled to the prescaler. 10=the vco is followed by a fixed divide by 2. 11=the vco is followed by a fixed divide by 4. this setting is used with the rf2722. pllx0(1:0) reserved 00 program to zero (0). location bit name default function pllx1(17:14) lpf_v(3:0) 3h vco coarse tune voltage pllx1(13:12) ct_noffs (1:0) 2h vco coarse tune offset adjustment pllx1(11:9) tlock(2:0) 3h kv calibration wait time pllx1(8:0) dn(8:0) 96h delta-n value for kv calibration
59 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution pll register x2 (pllx2) - address 000111 tx modulation register (txmod) - address 001000 pa ramp register 1 (parmp1) - address 001001 pa ramp register 2 (parmp2) - address 001010 location bit name default function pllx2(17:16) fbase(1:0) 00 base frequency 00=f base is 0hz 01=f base is 832mhz 1x=f base is 1664mhz see the offs register description for more information on setting the pll/vco frequency. pllx2(15:11) ct_def(4:0) 0 vco coarse tune coefficient pllx2(10:8) ct_moffs(2:0) 3h vco coarse tune offset pllx2(7:6) ctn(1:0) 01 vco coarse tune type 00=3 bits 01=4 bits (internal vco1 or external rf2722 vco) 10=5 bits (internal vco2) 11=reserved pllx2(5:0) kv_def(5:0) 20h kv calibration setting location bit name default function txmod(17) txad 0 tx interface mode 0=analog tx interface 1=digital tx interface txmod(16) reserved 0 reserved, program to zero (0) txmod(15) tx_de 0 differential encoder, used with digital tx interface 0=input data on mdi is not differentially encoded 1=input data on mdi is differentially encoded txmod(14) tx_inv 0 symbol polarity after differential encoding 0=data is not inverted 1=data is inverted txmod(13:8) phadj(5:0) 0 symbol clock phase offset offset=(phadj/13) s txmod(7:4) tx_thp(3:0) 0 tx analog interface, positive threshold tx _ txmod(3:0) tx_thn(3:0) 0 tx analog interface, negative threshold tx _ location bit name default function parmp1(17:10) pat(7:0) 9ah pa ramp delay, delay time from the rising edge on the txst pin to the start of the ramp. delay=pat*(12/13) s. parmp1(9:0) pag(9:0) 3aeh pa ramp gain, used as a scaling factor on the pa ramp waveform gain=(pag/1024) location bit name default function parmp2(17) txenio 1 txen pin direction 0=txen is input 1=txen is output, generated by pa ramping system parmp2(16) paen 1 pa ramp enable 0=disabled, dac1 is controlled by dac1en and dac1v 1=enabled, dac1 is controlled by pa ramp control system, initiated by a rising edge on txen or txst pins parmp2(15:14) reserved 0 reserved, program to zero (0) parmp2(13:6) txenu(7:0) 98h txen rising edge delay from txst delay=txenu*(12/13) s parmp2(5:0) txend(5:0) 6h txen falling edge delay from end of pa ramp delay=txend*(12/13) s thp 12.5 v pk ? () 2 ? thn 12.5 v pk ? () 2 ?
60 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution pa ramp registers 3 through 11 (parmp3-parmp11) - addresses 001011 to 010011 dac1 control register (dac1) - address 010100 dac2 control register (dac2) - address 010101 location bit name default function parmp3(17:16) reserved 0 reserved, program to zero (0) parmp3(15:6) par[0,9:0] see text pa ramp waveform, step 0 parmp3(5:0) par[1,9:4] see text pa ramp waveform, step 1 parmp4(17:14) par[1,3:0] see text pa ramp waveform, step 1, cont. parmp4(13:4) par[2,9:0] see text pa ramp waveform, step 2 parmp4(3:0) par[3,9:6] see text pa ramp waveform, step 3 parmp5(17:12) par[3,5:0] see text pa ramp waveform, step 3, cont. parmp5(11:2) par[4,9:0] see text pa ramp waveform, step 4 parmp5(1:0) par[5,9:8] see text pa ramp waveform, step 5 parmp6(17:10) par[5,7:0] see text pa ramp waveform, step 5, cont. parmp6(9:0) par[6,9:0] see text pa ramp waveform, step 6 parmp7(17:8) par[7,9:0] see text pa ramp waveform, step 7 parmp7(7:0) par[8,9:2] see text pa ramp waveform, step 8 parmp8(17:16) par[8,1:0] see text pa ramp waveform, step 8, cont. parmp8(15:6) par[9,9:0] see text pa ramp waveform, step 9 parmp8(5:0) par[10,9:4] see text pa ramp waveform, step 10 parmp9(17:14) par[10,3:0] see text pa ramp waveform, step 10, cont. parmp9(13:4) par[11,9:0] see text pa ramp waveform, step 11 parmp9(3:0) par[12,9:6] see text pa ramp waveform, step 12 parmp10(17:12) par[12,5:0] see text pa ramp waveform, step 12, cont. parmp10(11:2) par[13,9:0] see text pa ramp waveform, step 13 parmp10(1:0) par[14,9:8] see text pa ramp waveform, step 14 parmp11(17:10) par[14,7:0] see text pa ramp waveform, step 14, cont. parmp11(9:0) par[15,9:0] see text pa ramp waveform, step 15 location bit name default function dac1(17) dac1en 0 dac1 enable, this bit unconditionally turns on dac1. should be programmed to zero (0) for normal pa operation (paen=1). 0=disable 1=enabled dac1(16) txenfsd 0 txen failsafe disable. the failsafe circuitry prevents txen from staying high for more than eight timeslots, to prevent pa damage. 0=txen failsafe circuit enabled 1=txen failsafe circuit disabled dac1(15:0) dac1v(15:0) 147bh dac1 value if paen=1, then dac1v(15:0) is used as the minimum value of the dac1/vramp pin output voltage. location bit name default function dac2(17) dac2en 0 dac2 enable 0=disable 1=enabled dac2(16) fnz 0 if programmed high, the modulation to the fractional divider is forced to zero. this is a test mode. dac2(15:0) dac2v(15:0) 0 dac2 value
61 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution calibration register (cal) - address 010110 tr switch control (trsw) - address 010111 location bit name default function cal(17:16) vcoi(1:0) 10 vco bias setting 00=current1 (lowest) 01=current2 10=current3 11=current4 (highest) cal(15) vsuen 0 vco bias startup inhibit 0=vco bias startup circuit is disabled 1=vco bias startup circuit is enabled cal(14:10) tvco(4:0) 8h vco warm-up time sets the time allotted for the vco to warm up before calibrations or other pll operations begin. warm-up time=tvco*(32/26e6) s cal(9) rc_en 1 rc calibration system enable 0=disabled 1=enabled cal(8:5) rcoffs(3:0) 0 rc calibration offset cal(4:0) rc_def(4:0) ch rc calibration default value location bit name default function trsw(17) regen 0 controls the dcad and dco regulators. program to zero in normal operation. trsw(16) dc_clk 0 dc offset correction clock 0=dc clock function disabled 1=26mhz clock is sent to rf2722 via the ldto pin for the amount of time set by dc_time3. this timer is activated by asserting rxen. trsw(15:10) reserved 0 reserved, program to zero (0) trsw(9:0) dc_time3(9:0) 51h sets the number of 26mhz clock cycles from the rising edge of tx_st or rx_en. these clocks are ported out of ldto to the front-end ic. programs in steps of tsymbol/3.
62 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution test register (test) - address 011110 location bit name default function test(17) tm_bit 0 test mode enable 0=normal functional mode 1=scan mode test(16:15) adtm(1:0) 00 adc test mode, routes the outputs of the i or q adcs to dri and drq pins 0x=normal mode 10=output of i adc quantizers are present on dri and drq 11=output of q adc quantizers are present on dri and drq test(14) txtest 0 transmit test enable, enables pn txdata sequence generator 0=disabled 1=enabled test(13) adtest 0 pll adc test mode 0=disabled 1=enabled test(12) reserved 0 reserved, program to zero (0) test(11:10) calsel(1:0) 00 calibration read back select 00=(cpr, vtc, kv) 01=(13?b0, rc) 10=(1?b0, di_fn) 11=(18?b0) test(9) reserved 0 reserved, program to zero (0) test(8) datest 0 pll dac test mode 0=disabled 1=enabled test(7) cpu 0 charge pump up 0=no effect 1=forces charge pumps to pump up (source) on pll1 and pll2 test(6) cpd 0 charge pump down 0=no effect 1=forces charge pumps to pump down (sink) on pll1 and pll2 test(5) ten 0 test mux enable 0=ldto pin provides output of serial interface 1=ldto pin provides output of test multiplexer test(4:3) tsel(1:0) 00 test mux selection 00=pll test mux 01=transmit test mux 1x=reserved test (2:0) tmux(2:0) 000 test multiplexer output selection, if tsel=00 then tmux is defined as: 000=lock detect 100=r divider output, fr 001=prescaler output 101=pump up 010=modulus control 110=pump down 011=n divider output, fv 111=lock detect if tsel=01 then tmux is defined as: 000=tx data 100=isample[1] 001=clk_tx_anin 101=isample[0] 010=sample_iq 110=qsample[1] 011=sample_mdi 111=qsample[0]
63 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution reset - address 011111 calibration register 2 (cal2) - address 110000 location bit name default function reset (17:0) reserved 0 reserved, program to zero (0) the rf6001 ic is forced into reset (default state) when the reset address is writ- ten. the part is held in reset until the ssb signal is taken high after the address is written. location bit name default function cal2(17:15) reserved 0 reserved, program to zero (0). cal2(14) r0816b 0 if programmed high, then every other par starting with par[1] is used to form the ramp. this shortens the ramping time to 8 quarter symbol times. if programmed low, the ramping time is 16 quarter symbol times. cal2(13) ealgn 0 resets the gmsk modulator symbol ra ster when the modulator input transitions from g_def to user data. this can by used in conjunction with g_dly to allow finer con- trol of the gmsk modulator latency. 0=gmsk modulator symbol raster set by txst 1=gmsk modulator symbol raster set by user data cal2(12:0) reserved 0 reserved, program to zero (0).
64 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution ssi - address 110001 location bit name default function ssi(17:16) clkrm(1:0) 00 clkr mode 0=clkr is enabled when enr=1, but operates only during the active data portion of the transfer (disabled during any blank data portion). 01=clkr is enabled when enr=1 and remains on regardless of the state of dbl. 1x=clkr is always disabled. ssi(15) rxckb 0 receive clock source 0=clkr is an output 1=clkr is an input ssi(14) rxfsb 0 receive frame sync source 0=fsr is an output 1=fsr is an input ssi(13) fs_loc 0 frame sync location 0=fsr coincident wi th msb of i data 1=fsr occurs on clock before msb of i data ssi(12) en_sel 0 receive ssi mode 0=rxssi starts with enr 1=rxssi starts with rxen ssi(11) rx_t 0 rxssi trailing clock pulses. adds clocks to the end of an rxssi transfer. 0=no extra clock cycles are added to the end of an rxssr transfer. 1=5 extra clock cycles are added to the end of an rxssr transfer. ssi(10) clkrinv 0 inverts the clkr signal. 0=uninverted, normal polarity 1=inverted polarity ssi(9) txd_mode 0 tx digital interface mode 0=digital tx interface, mck and ms are outputs 1=digital tx interface, mck and ms are inputs ssi(8:7) txf(1:0) 00 controls the fifo interface modes 00=tx fifo disabled 01=no ms mode. fifo will shift in bits on every falling edge of mck, regardless of the ms signal. 10=ms frame mode. fifo will shift in bits on every falling edge of mck, if ms is high. 11=ms pulse mode. at every ms pulse, the fifo will shift in a predetermined number of bits. the position of ms, relative to the first data bit is controlled by ms_loc. the number of bits shifted in is determined by ms_len[4:0]. ssi(6) txckinv 0 tx clock invert 0=data is latched on the falling edge of mck 1=data is latched on the rising edge of mck ssi(5) intnen 0 test bit. program to 0. ssi(4:1) ms_len(3:0) 0 ms pulse length. in txf=11 mode, ms_len controls the number of bits the tx fifo will shift in, on every ms pulse. ms_len=0: 4 bits ms_len=6: 10 bits ms_len=12: 24 bits ms_len=1: 5 bits ms_len=7: 11 bits ms_len=13: 26 bits ms_len=2: 6 bits ms_len=8: 12 bits ms_len=14: 32 bits ms_len=3: 7 bits ms_len=9: 13 bits ms_len=15: 48 bits ms_len=4: 8 bits ms_len=10: 14 bits ms_len=5: 9 bits ms_len=11: 16 bits ssi(0) ms_loc 0 ms pulse location 0=transfer of first data bit occurs on same clock period as the pulse on ms 1=transfer of first data bit occurs on the next clock period after the pulse on ms
65 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution rx blanking (blank) - address 110011 delay - address 110100 tx data control (dfill) - address 110101 location bit name default function blank (17) msr 0 controls the behavior of the ms pulse in a gprs serial tx burst, if the rf6001 is the bus master. if msr is high, then an ms pulse will occur every 16mck clock pulse, even between gprs bursts. if msr is low, the ms pulse will appear with the first mck pulse of each burst, regardless of how mc k pulses have elapsed since the last ms pulse. 0=ms resume disabled 1=ms resume enabled blank (16:14) g_cnt(2:0) 000 this field allows variable blanking of user data bits. in fifo, this bit is only active in ms pulse mode (txf=2). on the rising edge of ms, the fifo will ignore the first gcnt bits on the serial interface. in tx serial mode, the gmsk differential encoder and modulator will ignore the first gcnt bits. during this time, g_def will be gated to the modulator. in gprs mode, gcnt is only active in the first burst. blank (13) de_init 0 power on default of the differential encoder starting value. blank (12) reserved 0 reserved, program to zero (0). blank (11:6) blk_dly(5:0) 18h channel filter blanking delay. delay=blk_dly*3.69us. blank (5:0) agc_dly(5:0) 26h rx output bl anking delay. delay=agc_dly*3.69us. location bit name default function delay (17) aden_2 1 second dc correction system enable delay (16) ad2en_2 1 second dc correction system enable 2 0=dc correction system will continue to operate after the adapt time is elapsed, at the rate defined by adclk. 1=dc correction will stop at the end of the adapt time. delay (15:14) adcclk_2 (1:0) 11 dc correction system clock rate, after adapt time is elapsed. default is 13mhz/48, for slowest adapt. 00=13mhz 01=13mhz/2 10=13mhz/24 11=13mhz/48 delay (13:8) dcad_2(5:0) 25h fine dc correction fast adapt time. programs in steps of (48/13)us. default is 70us. delay (7:0) reserved 0 reserved, program to zero (0). location bit name default function dfill (17) fclr 0 if fclr is set high, the fifo will be cleared. once the operation is complete, the sdi bit will automatically revert low. dfill (16) g_def 0 g_def is the input value to the gmsk modulator when the modulator data input is not active. dfill (15) reserved 0 reserved, program to zero (0). dfill (14:10) g_dly(4:0) 0 this field will increase the latency of the gmsk modulator in 1/16 symbol increments. the modulator delay can be adjusted from 12.2 quarter symbol times (qst) to 19.95qst. g_dly cannot be used without ealgn. dfill (9:5) rd_dly(4:0) 0 in uam mode, rd_dly can be used to delay the ramp down in 1/8s increments, relative to the falling edge of txst. this field is not used if uam is low. dfill (4:0) ru_dly(4:0) 0 in uam mode, ru_dly can be used to delay the ramp up in 1/8s increments, relative to the rising edge of txst. note that this field is only used in gprs mode because pat always controls the first ramp up delay.
66 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution tx_dly - address 110110 location bit name default function tx_dly (17:9) md_dly2(8:0) 0 in a gprs transmission, with uam=0, when tx_st falls at the end of the present tx timeslot, the data from the fifo stops af ter the present data symbol completes and the value of g_def is used until md_dly2 expires. md_dly2 timing begins in this mode with the end of the symbol after the fall of tx_st. if uam is true then data flow restarts after md_dly2 expires after the rising edge of tx_st. in this mode md_dly2 is timed from the rising edge of tx_st. tx_dly (8:0) md_dly1(8:0) 0 sets the delay in 1/8 symbol time increments from the first rising edge of tx_st to the start of data into the modulator. g_def fill s the input data before md_dly1. in serial mode, md_dly1 functions only if mck is an output from the rf6001.
67 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution pcb design requirements pcb surface finish the pcb surface finish used for rfmd?s qualification process is electroless nickel, immersion gold. typical thickness is 3 inch to 8 inch gold over 180 inch nickel. pcb land pattern recommendation pcb land patterns are based on ipc-sm-782 standards when po ssible. the pad pattern shown has been developed and tested for optimized assembly at rfmd; however, it may require so me modifications to address co mpany specific assembly pro- cesses. the pcb land pattern has been develope d to accommodate lead and package tolerances. pcb metal land pattern a = 0.64 x 0.28 (mm) typ. b = 0.28 x 0.64 (mm) typ. c = 5.50 (mm) sq. 5.50 typ. 0.50 typ. pin 48 pin 1 pin 36 pin 24 b b b b b b b b b b b b c a a a a a a a a a a a a a a a a a a a a a a a a b b b b b b b b b b b b dimensions in mm. 0.50 typ. 0.55 typ. 2.75 0.55 typ. 5.50 typ. 2.75 figure 17. pcb metal land pattern (top view)
68 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution pcb solder mask pattern liquid photo-imageable (lpi) so lder mask is recommended. the solder mask footprint will match what is shown for the pcb metal land pattern with a 3mil expansion to accommodate sold er mask registration clearance around all pads. the center- grounding pad shall also have a solder ma sk clearance. expansion of the pads to create solder mask clearance can be pro- vided in the master data or requested from the pcb fabrication supplier. thermal pad and via design the pcb metal land pattern has been design ed with a thermal pad that matches the exposed die paddle size on the bottom of the device. thermal vias are required in the pcb layout to effectively conduct heat away from the package. the via pattern has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing strategies. the via pattern used for the rfmd qualification is based on th ru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025mm pl ating on via walls. if micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results. a = 0.74 x 0.38 (mm) typ. b = 0.38 x 0.74 (mm) typ. c = 5.60 (mm) sq. dimensions in mm. pin 48 pin 1 pin 36 pin 24 b b b b b b b b b b b b a a a a a a a a a a a a b b b b b b b b b b b b c a a a a a a a a a a a a 5.50 typ. 0.50 typ. 0.50 typ. 0.55 typ. 2.75 0.55 typ. 5.50 typ. 2.75 figure 18. pcb solder mask pattern (top view)
69 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution revision data rev eng changes prelim 040414 ly specification table power supply, maximu m current by pin: added four rows under this heading. application information power supplies and control signals: replaced with ?general purpose output control? and ?power supplies and control signals?. register tables rf6001 register map, calibration (cal): changed data from ?cal 5(17:0)? to ?cal(17:0)?. rf6001 register map, tx data (txdt): deleted row. rf6001 register map, calibration 2 (cal2): added row. rf6001 register map, blank (blank): added row. rf6001 register map, delay (delay): added row. rf6001 register map, d_fill (d_fill): added row. rf6001 register map, tx_dly (tx_dly): added row. prelim 040310 ly initial datasheet. (based on 6001-29, revision code prelim 040309.) reasons for new revision: ? improved osco driver swing and load capability. (the level of the clock drive was too low into the capacitive load which was presented to it by some customers. the specification on this revision is to be able to drive a capacitive load up to 30pf.) ? the txdt register was removed. ? changed default value of tlock to ?3?d3?. ? added msksel bit in cfg1(11). ? pll and phase detector changes to improve slew rate and overall settle time. (kv_def is now used for kv_val during kv calibration.) ? afc dac output is tri-stated when dac2en bit is low. specification table pll specification, frequency range, internal : added line with min specification of ?0mhz? and max specification of ?2100mhz?. pll specification, frequency range, fin pin : existing line with min specification of ?0mhz? and max specification of ?550mhz?. oscillator output buff er, output voltage (v out ) : changed min specification from ?600mv p-p ? to ?800mv p-p ?. oscillator output buffer, load capacitance : changed min specification from ?1pf? to ?5pf?, and max specifica- tion from ?10pf? to ?30pf?. dac1 and dac2 specifications, dac2 (afc) tri-state output impedance : added. application information transmit modulation interface digital mode : added second and fourth paragraphs. addition of delay on mck : added. transmit test modes : changed to ?transmit test mode?; first paragr aph updated to reflect single test mode, and ?txtest=1, txtm=0? added to first paragraph; ?txtest=1, txtm=1? section removed. register tables cfg1, cfg1(11:10) : changed to ?cfg1(10)?. cfg1, cfg1(11) : added as ?mcksel? bit. pllx1, plllx1(11:9) : default value changed from ?0? to ?3h?. txdt : table removed. prelim 040317 ly application information synthesizer information, vco?s: replaced two paragraphs following table with one paragraph; updated diagram. rev a0 040930 jm banner : changed from ?proposed? to ?preliminary?. pcb design requirements : added. rev a1 041118 jm banner : ?preliminary? banner removed. trademark information : added. rev a2 050602 pb application information analog i/q mode: replaced first paragraph with seven new paragraphs and a table. register tables txmod, txmod(7:4): changed equation. txmod, txmod(3:0): changed equation. rev a3 050929 admin ?rohs-compliant & pb-free? notation and rohs information added.
70 of 70 rf6001 rev a3 ds050929 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . part of the polaris? total radio? solution

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